公开(公告)号：US09412655B1

公开(公告)日：2016-08-09

申请号：US14608377

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason E. Stephens ,  Vikrant Chauhan ,  Andy C. Wei

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/308 ,  H01L21/033

CPC classification number: H01L21/3081 ,  H01L21/0334 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897

Abstract: A method includes forming a plurality of sacrificial lines embedded in a first dielectric layer. A line merge opening and a line cut opening are formed in a hard mask layer formed above the first dielectric layer. Portions of the first dielectric layer exposed by the line merge opening are removed to define a line merge recess. A portion of a selected sacrificial line exposed by the line cut opening is removed to define a line cut recess between first and second segments of the selected sacrificial line. A second dielectric layer is formed in the line cut recess. The hard mask is removed. The plurality of sacrificial lines is replaced with a conductive material to define at least one line having third and fourth segments in locations previously occupied by the first and second segments and to define a line-merging conductive structure in the line merge recess.

Abstract translation: 一种方法包括形成埋在第一介电层中的多条牺牲线。 在形成在第一电介质层上方的硬掩模层中形成线合并开口和线切口。 去除由线合并开口露出的第一电介质层的部分以限定线合并凹槽。 通过线切割开口暴露的所选牺牲线的一部分被去除以在所选牺牲线的第一和第二段之间限定线切割凹槽。 第二介质层形成在线切割凹部中。 硬面膜被去除。 多个牺牲线被导电材料代替，以限定在先前由第一和第二段占据的位置中限定具有第三和第四段的至少一个线，并且在线合并凹槽中限定线路合并导电结构。

公开(公告)号：US20160225666A1

公开(公告)日：2016-08-04

申请号：US14608377

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason E. Stephens ,  Vikrant Chauhan ,  Andy C. Wei

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/3081 ,  H01L21/0334 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897

Abstract: A method includes forming a plurality of sacrificial lines embedded in a first dielectric layer. A line merge opening and a line cut opening are formed in a hard mask layer formed above the first dielectric layer. Portions of the first dielectric layer exposed by the line merge opening are removed to define a line merge recess. A portion of a selected sacrificial line exposed by the line cut opening is removed to define a line cut recess between first and second segments of the selected sacrificial line. A second dielectric layer is formed in the line cut recess. The hard mask is removed. The plurality of sacrificial lines is replaced with a conductive material to define at least one line having third and fourth segments in locations previously occupied by the first and second segments and to define a line-merging conductive structure in the line merge recess.

Abstract translation: 一种方法包括形成埋在第一介电层中的多条牺牲线。 在形成在第一电介质层上方的硬掩模层中形成线合并开口和线切口。 去除由线合并开口露出的第一电介质层的部分以限定线合并凹槽。 通过线切割开口暴露的所选牺牲线的一部分被去除以在所选牺牲线的第一和第二段之间限定线切割凹槽。 第二介质层形成在线切割凹部中。 硬面膜被去除。 多个牺牲线被导电材料代替，以限定在先前由第一和第二段占据的位置中限定具有第三和第四段的至少一个线，并且在线合并凹槽中限定线路合并导电结构。

公开(公告)号：US20200152531A1

公开(公告)日：2020-05-14

申请号：US16425387

申请日：2019-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mankyu Yang ,  Vara Govindeswara Reddy Vakada ,  Edward Maciejewski ,  Brian Greene ,  Atsushi Ogino ,  Vikrant Chauhan ,  Prianka Sengupta

IPC: H01L21/66 ,  H01L23/522 ,  H01L23/528 ,  G01R31/26

Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.

公开(公告)号：US20200152530A1

公开(公告)日：2020-05-14

申请号：US16185696

申请日：2018-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mankyu Yang ,  Vara Govindeswara Reddy Vakada ,  Edward Maciejewski ,  Brian Greene ,  Atsushi Ogino ,  Vikrant Chauhan ,  Prianka Sengupta

IPC: H01L21/66 ,  H01L23/528 ,  H01L21/768

Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a test pad, a device-under-testing having one or more source/drain regions, and a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines that are connected with the test pad. One or more contacts, which are arranged between the metallization level and the device-under-testing, directly connect the one or more interconnect lines with the one or more source/drain regions.

公开(公告)号：US20180269275A1

公开(公告)日：2018-09-20

申请号：US15463465

申请日：2017-03-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Atsushi Ogino ,  Vikrant Chauhan ,  Kong Boon Yeap ,  Ahmed Hassan

IPC: H01L49/02

CPC classification number: H01L28/88

Abstract: Structures for an on-chip capacitor and methods of forming an on-chip capacitor. A metal terminal is formed that has a side edge. Metal fingers are formed that have a parallel arrangement. Floating islands comprised of a metal are formed and are electrically isolated from the metal fingers. Each of the metal fingers has an end and extends from the side edge of the metal terminal toward the end. Each of the floating islands is arranged in a spaced relationship with the end of a respective one of the metal fingers.

公开(公告)号：US10078107B2

公开(公告)日：2018-09-18

申请号：US14924439

申请日：2015-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jaime Bravo ,  Vikrant Chauhan ,  Ryan Scott Smith

IPC: G01R31/26 ,  G01R31/28

CPC classification number: G01R31/2607 ,  G01R31/2601 ,  G01R31/2831 ,  G01R31/2884

Abstract: Three reference resistors of the same resistance and a test structure are connected in a circuit having a Wheatstone Bride design. The circuit is electrically coupled between an input and ground. A voltage applied at the input resulting in an electrical characteristic difference between two midpoints of the circuit indicates the need for corrective action with respect to a design of the test structure for either OPC or etch bias.

公开(公告)号：US09465907B2

公开(公告)日：2016-10-11

申请号：US14341092

申请日：2014-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ahmed Hassan ,  Nader Magdy Hindawy ,  Vikrant Chauhan ,  Jason Eugene Stephens ,  David Pritchard ,  Abbas Guvenilir ,  David E. Brown ,  Terry J. Bordelon, Jr.

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5072

Abstract: One illustrative method disclosed herein involves, among other things, decomposing an initial circuit layout into first and second mask patterns, for the first mask pattern, identifying a first four-polygon pattern in the first mask pattern that violates a multi-polygon constraint rule, wherein the first four-polygon pattern comprises four polygons positioned side-by-side in the first mask pattern, and recoloring one or two of the polygons in the first four-polygon pattern in the first mask pattern to the second mask pattern to eliminate the first four-polygon pattern from the first mask pattern without introducing any design rule violations in the initial circuit layout.

Abstract translation: 本文公开的一种说明性方法涉及对于第一掩模图案将初始电路布局分解为第一和第二掩模图案，识别违反多边形约束规则的第一掩模图案中的第一四边形图案， 其中所述第一四面体图案包括在所述第一掩模图案中并排定位的四个多边形，以及将所述第一掩模图案中的所述第一四面体图案中的一个或两个多边形重新染色到所述第二掩模图案以消除 在第一掩模图案中的第一四面多边形图案，而不会在初始电路布局中引入任何设计规则违规。

公开(公告)号：US20160026748A1

公开(公告)日：2016-01-28

申请号：US14341092

申请日：2014-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ahmed Hassan ,  Nader Magdy Hindawy ,  Vikrant Chauhan ,  Jason Eugene Stephens ,  David Pritchard ,  Abbas Guvenilir ,  David E. Brown ,  Terry J. Bordelon, Jr.

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5072

Abstract: One illustrative method disclosed herein involves, among other things, decomposing an initial circuit layout into first and second mask patterns, for the first mask pattern, identifying a first four-polygon pattern in the first mask pattern that violates a multi-polygon constraint rule, wherein the first four-polygon pattern comprises four polygons positioned side-by-side in the first mask pattern, and recoloring one or two of the polygons in the first four-polygon pattern in the first mask pattern to the second mask pattern to eliminate the first four-polygon pattern from the first mask pattern without introducing any design rule violations in the initial circuit layout.

Abstract translation: 本文公开的一种说明性方法涉及对于第一掩模图案，将初始电路布局分解为第一和第二掩模图案，识别违反多边形约束规则的第一掩模图案中的第一四边形图案， 其中所述第一四面体图案包括在所述第一掩模图案中并排定位的四个多边形，以及将所述第一掩模图案中的所述第一四面体图案中的一个或两个多边形重新染色到所述第二掩模图案以消除 在第一掩模图案中的第一四面多边形图案，而不会在初始电路布局中引入任何设计规则违规。

公开(公告)号：US20150050811A1

公开(公告)日：2015-02-19

申请号：US14527129

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sohan Mehta ,  Tong Qing Chen ,  Vikrant Chauhan ,  Ravi Srivastava ,  Catherine Labelle ,  Mark Kelling

IPC: H01L21/311

CPC classification number: H01L21/311 ,  H01L21/31144 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.

Abstract translation: 本文公开了包括多个第一线特征和多个第二线特征的说明性测试结构。 在该实施例中，每个第二线特征具有第一和第二相对端，并且第一和第二线特征被布置成光栅图案，使得第一线特征的第一端对准以限定光栅结构的第一侧 并且第一特征的第二端对齐以限定与光栅结构的第一侧相对的光栅结构的第二侧。 第二线特征的第一端具有延伸超过光栅结构的第一侧的第一端，而第二线特征的第二端具有延伸超过光栅结构的第二侧的第一端。