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公开(公告)号：US10032510B2
公开(公告)日：2018-07-24
申请号：US15305309
申请日：2014-04-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： David B. Fujii , Yoocharn Jeon , Siamak Tavallaei
Abstract: A multimodal memristor memory provides selectable or reconfigurable operation in a plurality of operational modes of a memristor. The multimodal memristor memory includes a memristor having a plurality of operational modes. The multimodal memristor memory further includes a reconfigurable interface driver to select an operational mode of the plurality of operational modes of the memristor. The memristor is to operate in the operational mode selected by the reconfigurable interface driver.
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公开(公告)号：US09773547B2
公开(公告)日：2017-09-26
申请号：US15113914
申请日：2014-01-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Richard H. Henze , Naveen Muralimanohar , Yoocharn Jeon , Martin Foltin , Erik Ordentlich , Gregg B. Lesartre , R. Stanley Williams
CPC classification number: G11C13/004 , G11C5/025 , G11C11/005 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C2213/71 , G11C2213/72 , G11C2213/77 , G11C2213/79 , H01L23/528 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147
Abstract: A non-volatile memory device with multiple latency tiers includes at least two crossbar memory arrays, each crossbar memory array comprising a number of memory cells, each memory cell connected to a word line and a bit line at a cross point. The crossbar memory arrays each have a different latency. The crossbar memory arrays are formed on a single die.
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公开(公告)号：US20170271004A1
公开(公告)日：2017-09-21
申请号：US15500052
申请日：2015-02-24
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Yoocharn Jeon
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0007 , G11C13/0023 , G11C13/0033 , G11C2013/0045 , G11C2013/0054 , G11C2213/15
Abstract: In one example in accordance with the present disclosure a method of determining a state of a memristor in a crossbar array is described. In the method a bias voltage is applied to a target row line in the crossbar array, which bias voltage causes a bias current to pass through a target memristor along the target row line. The bias voltage is increased by a predetermined amount to a state voltage. A state current flowing through the target memristor is determined. The state current is based on the state voltage. A state of the target memristor is determined based on the state current.
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公开(公告)号：US20170271003A1
公开(公告)日：2017-09-21
申请号：US15500051
申请日：2015-02-24
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Yoocharn Jeon
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0033 , G11C2013/0054 , G11C2013/0057 , G11C2213/72
Abstract: In one example in accordance with the present disclosure a method of determining a resistance state of a memristor in a crossbar array is disclosed. In the method, a combined reference-sneak current is determined based on a reference voltage, a sense voltage, a non-access voltage, and a voltage applied to a target row line. Also in the method a combined read-sneak current is determined based on a read voltage, a sense voltage, a non-access voltage, and a voltage applied to a reference row line. A resistance state of a target memristor is determined based on the combined reference-sneak current and the combined read-sneak current.
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公开(公告)号：US20160351259A1
公开(公告)日：2016-12-01
申请号：US15111981
申请日：2014-01-24
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Yoocharn Jeon , Erik Ordentlich , Gregg B. Lesartre , Siamak Tavallaei
CPC classification number: G11C13/0069 , G06F11/1048 , G06F11/1068 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C29/12 , G11C29/52 , G11C2013/0076
Abstract: A memristor memory is disclosed. In an example, the memristor memory comprises a memristor component having a plurality of memristor cells. Each memristor cell is configured to change state based on application of an electric potential. The memristor memory also comprises a controller to read the state of the plurality of memristor cells and identify a subset of the plurality of memristor cells to rewrite. The controller writes the subset of the plurality of memristor cells, and the controller reads an updated state of the plurality of memristor cells to validate the subset was written correctly.
Abstract translation: 忆阻记忆体被公开。 在一个示例中，忆阻器存储器包括具有多个忆阻单元的忆阻器部件。 每个忆阻器单元被配置为基于施加电位而改变状态。 忆阻器存储器还包括控制器，用于读取多个忆阻单元的状态，并且识别多个忆阻器单元的子集以重写。 控制器写入多个忆阻器单元的子集，并且控制器读取多个忆阻器单元的更新状态以验证该子集被正确写入。
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Patent Agency Ranking
公开(公告)号：US10332595B2
公开(公告)日：2019-06-25
申请号：US15500051
申请日：2015-02-24
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Yoocharn Jeon
IPC: G11C13/00
Abstract: The resistance state of a memristor in a crossbar array is determined. For instance, a combined reference-sneak current is determined based on a reference voltage, a sense voltage, a non-access voltage, and a voltage applied to a target row line, and a combined read-sneak current is determined based on a read voltage, a sense voltage, a non-access voltage, and a voltage applied to a reference row line. The resistance state of a target memristor is then determined based on the combined reference-sneak current and the combined read-sneak current.
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公开(公告)号：US10056140B2
公开(公告)日：2018-08-21
申请号：US15112767
申请日：2014-01-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Yoocharn Jeon , Martin Foltin
CPC classification number: G11C13/0035 , G11C13/0002 , G11C13/0007 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C14/00
Abstract: In an example, a method of controlling a memristor memory includes operating the memristor memory in a volatile mode, wherein switching a state of a memristor cell is with a low writing load. The method also includes operating the same memristor memory in a non-volatile mode, wherein switching a state of the memristor cell is with a high writing load.
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公开(公告)号：US09947397B2
公开(公告)日：2018-04-17
申请号：US15329776
申请日：2014-09-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Yoocharn Jeon
CPC classification number: G11C13/0023 , G11C8/08 , G11C8/10 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C2013/0054 , G11C2213/77
Abstract: Example implementations disclosed herein can be used to decode memory elements in a crosspoint array. In one example implementation, crosspoint array decoder includes a number of field effect transistor decoder switches corresponding to specific lines in a crosspoint array and a sense amplifier coupled to at least some of the field effect transistor decoder switches and includes a set of inference field effect transistors matched to the field effect transistor decoder switches to infer a stimulus voltage applied to a memory element in a crosspoint array.
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公开(公告)号：US20170206959A1
公开(公告)日：2017-07-20
申请号：US15320817
申请日：2014-07-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Yoocharn Jeon
IPC: G11C13/00
CPC classification number: G11C13/0028 , G11C5/025 , G11C7/12 , G11C8/08 , G11C8/10 , G11C13/0026
Abstract: A crossbar array with shared drivers has a plurality of sets of row lines, a set of row drivers, a plurality of sets of column lines, a set of column drivers, and a plurality of memory cells. Each set of row lines has a plurality of row lines and is driven by a set of row drivers. Furthermore, each set of row lines intersects with a plurality of the sets of column lines. Likewise, each set of column lines has a plurality of column lines and is driven by a set of column drivers. Each set of column lines intersects with a plurality of the sets of row lines. Each memory cell is coupled between an intersection of a row line and a column line.
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公开(公告)号：US20170206956A1
公开(公告)日：2017-07-20
申请号：US15325040
申请日：2014-10-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Martin Foltin , Yoocharn Jeon , Brent Buchanan , Erik Ordentlich , Naveen Muralimanohar , James S. Ignowski , Jacquelyn M. Ingemi
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C7/06 , G11C13/0038 , G11C13/0059 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C27/024 , G11C2013/0045 , G11C2013/0054 , G11C2207/068
Abstract: This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.
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