公开(公告)号：US06661692B2

公开(公告)日：2003-12-09

申请号：US10179710

申请日：2002-06-24

申请人： Shinsuke Anzai ,  Kenji Kamei ,  Yasumichi Mori

发明人： Shinsuke Anzai ,  Kenji Kamei ,  Yasumichi Mori

IPC分类号： G11C506

CPC分类号： G11C29/80 ,  G11C15/00 ,  G11C15/046 ,  H01L27/0207

摘要： A semiconductor integrated circuit of the present invention includes: n first output circuits and m second output circuits which are provided such that adjacent first and second output circuits are spaced at a regular first pitch; and input circuits which are provided such that adjacent input circuits are spaced at a regular second pitch, in which the first and second output circuits are provided such that at least part of ones of the first and second output circuit blocks alternate with the other ones of the first and second output circuits and each of the first output circuits is connected to a corresponding one of input circuits by a first conductor line which is kept straight, and second conductor lines are connected to the second output circuits such that each second conductor line passes through a gap between the input circuits.

摘要翻译： 本发明的半导体集成电路包括：n个第一输出电路和m个第二输出电路，其被设置成使得相邻的第一和第二输出电路以规则的第一间距间隔开; 以及输入电路，其被设置为使得相邻输入电路以规则的第二间距间隔开，其中第一和第二输出电路被设置成使得第一和第二输出电路块中的至少一部分与其他 第一和第二输出电路和第一输出电路中的每一个通过保持直的第一导体线连接到相应的一个输入电路，并且第二导体线连接到第二输出电路，使得每个第二导线通过 通过输入电路之间的间隙。

公开(公告)号：US07184334B2

公开(公告)日：2007-02-27

申请号：US11051346

申请日：2005-02-04

申请人： Masahiko Watanabe ,  Yasumichi Mori

发明人： Masahiko Watanabe ,  Yasumichi Mori

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C13/0028 ,  G11C13/0007 ,  G11C29/26 ,  G11C29/76 ,  G11C2029/2602 ,  G11C2213/31

摘要： A semiconductor memory device comprises at least one memory plane in which a plurality of memory blocks are arranged, and a block decoder circuit which decodes a block address signal for selecting the memory block from the memory plane and outputs block selection signals for selecting the memory block, as well as puts all of the block selection signals in a selected state and output them in a predetermined test mode, and a block selection signal inversion circuit which inverts or non-inverts signal levels of the block selection signals.

摘要翻译： 半导体存储器件包括至少一个其中布置有多个存储器块的存储器平面;以及块解码器电路，用于解码用于从存储器平面选择存储块的块地址信号，并输出用于选择存储块的块选择信号 并且将所有块选择信号置于选择状态并以预定的测试模式输出;以及块选择信号反相电路，其对块选择信号的信号电平进行反相或非反相。

公开(公告)号：US07020037B2

公开(公告)日：2006-03-28

申请号：US11051139

申请日：2005-02-04

申请人： Shinsuke Anzai ,  Yasumichi Mori

发明人： Shinsuke Anzai ,  Yasumichi Mori

IPC分类号： G11C7/02

CPC分类号： G11C16/28 ,  G11C11/5642 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C16/3436 ,  G11C2013/0054 ,  G11C2213/31

摘要： A nonvolatile semiconductor memory device includes a readout circuit which reads data stored in a selected memory cell by applying predetermined voltage to the selected memory cell and a reference cell such that currents corresponding to the respective threshold voltage may flow, and comparing the current flowing in the selected memory cell with the current flowing in the reference cell. The readout circuit commonly uses the reference cell set in the same storage state for normal readout and for readout for program verification, and when the predetermined voltage is applied to the selected memory cell and the reference memory cell at the time of the readout for the program verification, it sets an applying condition to the reference memory cell such that its storage state may be shifted more in the program state direction than that in an applying condition at the time of the normal readout.

摘要翻译： 非易失性半导体存储器件包括：读出电路，通过向所选择的存储单元施加预定电压，读取存储在所选择的存储单元中的数据;以及参考单元，使得与各个阈值电压相对应的电流可以流动， 选定的存储单元，电流在参考单元中流动。 读出电路通常使用相同存储状态的参考单元设置用于正常读出和用于程序验证的读出，并且当在用于程序的读出时将预定电压施加到所选择的存储单元和参考存储单元时 验证时，将参考存储单元的应用条件设置为使得其存储状态可以在程序状态方向上比在正常读出时的应用条件中更多地移位。

公开(公告)号：US20050174862A1

公开(公告)日：2005-08-11

申请号：US11051346

申请日：2005-02-04

申请人： Masahiko Watanabe ,  Yasumichi Mori

发明人： Masahiko Watanabe ,  Yasumichi Mori

IPC分类号： G11C16/02 ,  G11C8/12 ,  G11C11/15 ,  G11C13/00 ,  G11C16/08 ,  G11C29/00 ,  G11C29/04 ,  G11C29/14 ,  G11C29/26 ,  G11C29/56 ,  G11C7/00

CPC分类号： G11C13/0028 ,  G11C13/0007 ,  G11C29/26 ,  G11C29/76 ,  G11C2029/2602 ,  G11C2213/31

摘要： A semiconductor memory device comprises at least one memory plane in which a plurality of memory blocks are arranged, and a block decoder circuit which decodes a block address signal for selecting the memory block from the memory plane and outputs block selection signals for selecting the memory block, as well as puts all of the block selection signals in a selected state and output them in a predetermined test mode, and a block selection signal inversion circuit which inverts or non-inverts signal levels of the block selection signals.

摘要翻译： 半导体存储器件包括至少一个其中布置有多个存储器块的存储器平面;以及块解码器电路，用于解码用于从存储器平面选择存储块的块地址信号，并输出用于选择存储块的块选择信号 并且将所有块选择信号置于选择状态并以预定的测试模式输出;以及块选择信号反相电路，其对块选择信号的信号电平进行反相或非反相。

公开(公告)号：US06400602B2

公开(公告)日：2002-06-04

申请号：US09818194

申请日：2001-03-26

申请人： Hidekazu Takata ,  Kengo Maeda ,  Yasumichi Mori

发明人： Hidekazu Takata ,  Kengo Maeda ,  Yasumichi Mori

IPC分类号： G11C1606

CPC分类号： G11C29/76 ,  G11C29/88 ,  G11C29/883

摘要： A semiconductor memory device includes: a plurality of memory cell regions, each comprising at least one memory cell; a non-volatile memory section which accepts external writing; and unselecting means for designating at least one of the plurality of memory cell regions to be inaccessible based on data written to the non-volatile memory section. At least one operation type is performed for at least one accessible memory cell region, which is not designated to be inaccessible, among the plurality of memory cell regions.

摘要翻译： 半导体存储器件包括：多个存储单元区域，每个存储单元区域包括至少一个存储单元; 接受外部写入的非易失性存储器部分; 以及取消选择装置，用于基于写入所述非易失性存储器部分的数据来指定所述多个存储器单元区域中的至少一个是不可访问的。 对于多个存储单元区域中的至少一个不被指定为不可访问的可访问存储单元区域执行至少一种操作类型。

公开(公告)号：US4256531A

公开(公告)日：1981-03-17

申请号：US876612

申请日：1978-02-10

申请人： Shigeyuki Kimura ,  Isamu Shindo ,  Yasumichi Mori ,  Kenji Kitamura ,  Nobuo Ii

发明人： Shigeyuki Kimura ,  Isamu Shindo ,  Yasumichi Mori ,  Kenji Kitamura ,  Nobuo Ii

IPC分类号： C30B13/00 ,  C30B13/02

CPC分类号： C30B13/02 ,  C30B13/00 ,  C30B29/28

摘要： A single crystal of yttrium-iron garnet or solid solution comprising aluminum oxide component, gallium oxide component, iron oxide and/or the other rare earth oxide component is produced by a floating zone method.

摘要翻译： 通过浮区法制造钇 - 铁石榴石或包含氧化铝组分，氧化镓组分，氧化铁和/或其它稀土氧化物组分的单晶。

公开(公告)号：US20070279984A1

公开(公告)日：2007-12-06

申请号：US10589101

申请日：2005-02-09

申请人： Yasumichi Mori ,  Masahiko Watanabe

发明人： Yasumichi Mori ,  Masahiko Watanabe

IPC分类号： G11C11/34

CPC分类号： G11C29/76

摘要： A nonvolatile semiconductor storing device according to the present invention comprises a block replacing means for replacing a defective block with a redundant block when a memory block in a memory array is the defective block. The block replacing means includes an address translation circuit 10 for converting an inputted external block address into an internal block address by inverting an address bit corresponding to dissident of each address bit between a defective block address of the defective block and a redundant block address among address bits of the inputted external block address, and each of the memory blocks 5 is selected based on the internal block address after the translation of the external block address inputted from outside by the address translation circuit 10.

摘要翻译： 根据本发明的非易失性半导体存储装置包括：块存储器替换装置，用于在存储器阵列中的存储块是缺陷块时用冗余块替换缺陷块。 块替换装置包括地址转换电路10，用于将输入的外部块地址转换为内部块地址，通过将与缺陷块的缺陷块地址和地址中的冗余块地址之间的每个地址位的不同位相对应的地址位反相 基于由地址转换电路10从外部输入的外部块地址的转换之后的内部块地址来选择输入的外部块地址的比特，并且存储块5中的每一个被选择。

公开(公告)号：US06930922B2

公开(公告)日：2005-08-16

申请号：US10630568

申请日：2003-07-29

申请人： Yasumichi Mori ,  Takahiko Yoshimoto ,  Shinsuke Anzai ,  Takeshi Nojima

发明人： Yasumichi Mori ,  Takahiko Yoshimoto ,  Shinsuke Anzai ,  Takeshi Nojima

IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/04 ,  G11C16/28

CPC分类号： G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

摘要： A reading circuit, for reading data from one memory cell of a plurality of memory cells, includes a plurality of division sensing circuits each connected to the one memory cell via a sensing line corresponding thereto among a plurality of sensing lines; and a current-voltage conversion circuit for converting a current flowing through each sensing line into a sensing voltage representing a potential of the corresponding sensing line. Each division sensing circuit includes a current load circuit for supplying a current to the one memory cell via a corresponding sensing line, and a sense amplifier for sensing a potential difference between the corresponding sensing line and a corresponding reference line of a plurality of reference lines. The current load circuit included in at least one division sensing circuit has a current supply capability different from that of the current load circuit included in another division sensing circuits.

摘要翻译： 读取电路，用于从多个存储单元的一个存储单元读取数据，包括多个分割感测电路，每个分割感测电路经由多个感测线路中与之对应的感测线连接到该一个存储单元; 以及电流 - 电压转换电路，用于将流过每个感测线的电流转换成表示相应感测线的电位的感测电压。 每个分割感测电路包括用于经由相应的感测线路向一个存储单元提供电流的电流负载电路和用于感测相应感测线与多条参考线的对应参考线之间的电位差的读出放大器。 包括在至少一个分割感测电路中的电流负载电路具有与包括在另一个分割感测电路中的当前负载电路不同的电流供应能力。

公开(公告)号：US20050174859A1

公开(公告)日：2005-08-11

申请号：US11055641

申请日：2005-02-09

申请人： Yasumichi Mori ,  Takahiko Yoshimoto ,  Masahiko Watanabe ,  Shinsuke Anzai ,  Takeshi Nojima ,  Munetaka Masaki

发明人： Yasumichi Mori ,  Takahiko Yoshimoto ,  Masahiko Watanabe ,  Shinsuke Anzai ,  Takeshi Nojima ,  Munetaka Masaki

IPC分类号： G11C16/06 ,  G11C7/06 ,  G11C7/12 ,  G11C16/28 ,  G11C29/02 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C16/28 ,  G11C7/06 ,  G11C7/062 ,  G11C7/12 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5004 ,  G11C2207/063

摘要： Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.

摘要翻译： 向所选存储单元和参考存储单元提供电流的两个偏置电路具有相同的电路结构。 每个偏置电路包括在电源节点和接合节点之间的第一有源元件，其中电流被控制以防止接合节点处的电压电平波动，电源节点和输出节点之间的第二有源元件，其中 控制电流使得输出节点处的电压电平在与其他偏置电路中的连接节点处的电压电平相反的方向上改变，第三有源元件和第四有源元件在接合节点和电流供应节点之间，以及 分别在输出节点和电流供应节点之间调整偏置电压。

公开(公告)号：US06912161B2

公开(公告)日：2005-06-28

申请号：US10611643

申请日：2003-07-02

申请人： Yasuaki Hirano ,  Yasumichi Mori ,  Shuichiro Kouchi

发明人： Yasuaki Hirano ,  Yasumichi Mori ,  Shuichiro Kouchi

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C16/06 ,  G11C16/10 ,  G11C16/28

CPC分类号： G11C11/5642 ,  G11C16/10 ,  G11C16/28 ,  G11C2211/5634

摘要： In the nonvolatile semiconductor memory device of this invention, a program control circuit 1 sets the threshold value of a first reference cell RFC0 by means of a write circuit WC on the basis of a result of comparing the threshold value of the first reference cell RFC0 with the threshold value of a second reference cell SRC executed by a sense amplifier 8 for trimming. The compare of threshold values by the sense amplifier 8 for trimming can be executed within a shorter time than in the threshold value read operation of the first reference cell RFC0. Therefore, when the number of the first reference cells is increased, the threshold value adjustment time can be remarkably reduced in comparison with the prior art in which the threshold value of the first reference cell is adjusted by reading the first reference cell.

摘要翻译： 在本发明的非易失性半导体存储器件中，程序控制电路1基于比较第一参考单元RFC的阈值的结果，通过写入电路WC来设置第一参考单元RFC0的阈值 0与用于修整的读出放大器8执行的第二参考单元SRC的阈值。 可以在比第一参考单元RFC 0的阈值读取操作更短的时间内执行用于修整的读出放大器8的阈值的比较。因此，当第一参考单元的数量增加时，阈值 与通过读取第一参考单元来调整第一参考单元的阈值的现有技术相比，可以显着地减小调整时间。