公开(公告)号：US06878586B2

公开(公告)日：2005-04-12

申请号：US10458271

申请日：2003-06-11

申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45 ,  H01L21/8242

CPC分类号： H01L27/10817 ,  H01L27/10808 ,  H01L29/41775 ,  H01L29/456

摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

公开(公告)号：US5591998A

公开(公告)日：1997-01-07

申请号：US443106

申请日：1995-05-17

申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L27/10808 ,  H01L27/10817 ,  H01L29/41775 ,  H01L29/456

摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

公开(公告)号：US5583358A

公开(公告)日：1996-12-10

申请号：US324352

申请日：1994-10-17

申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L27/10808 ,  H01L27/10817 ,  H01L29/41775 ,  H01L29/456

摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

公开(公告)号：US5140389A

公开(公告)日：1992-08-18

申请号：US475148

申请日：1990-02-05

申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

IPC分类号： H01L27/108

CPC分类号： H01L27/10817

摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacitor portions to be arranged very densely and a sufficiently large capacitance to be maintained with very small cell areas. Since the storage capacitor portions are formed even on the bit lines, the bit lines are shielded, so that the capacitance decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacitor portion so that a part thereof is in the form of a wall substantially vertical to the substrate in order to increase the capacitance.

摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储电容器 要非常密集地布置的部分和足够大的电容以保持非常小的电池区域。 由于存储电容器部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的电容减小，因此存储器阵列噪声减小。 也可以设计电荷存储电容器部分，使得其一部分呈基本上垂直于衬底的壁的形式，以增加电容。

公开(公告)号：US4797717A

公开(公告)日：1989-01-10

申请号：US039291

申请日：1987-04-17

申请人： Koichiro Ishibashi ,  Osamu Minato ,  Toshiaki Masuhara ,  Yoshio Sakai ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Shoji Hanamura ,  Nobuyuki Moriwaki ,  Shigeru Honjyo ,  Kiyotsugu Ueda

发明人： Koichiro Ishibashi ,  Osamu Minato ,  Toshiaki Masuhara ,  Yoshio Sakai ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Shoji Hanamura ,  Nobuyuki Moriwaki ,  Shigeru Honjyo ,  Kiyotsugu Ueda

IPC分类号： G11C11/403 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/10 ,  H01L27/11 ,  H01L29/45 ,  H01L29/78 ,  H01L27/02 ,  H01L29/04

CPC分类号： H01L29/456 ,  H01L27/1112 ,  Y10S257/904

摘要： Each of the memory cells in a SRAM includes two driver MOS transistors, two transfer gate MOS transistors and two load resistances. The gate electrode layers of the MOS transistors are formed from a first-level conductive layer provided on the surface of a semiconductor substrate. The source regions of the two driver MOS transistors in each memory cell are connected in common and further connected to a ground potential point through a second-level conductive layer. The two load resistances in each memory cell are formed from a third-level high-resistance material layer. The second-level conductive layer is formed from a low-resistance material layer. Thus the resistance of the sources of the two driver MOS transistors is lowered.

摘要翻译： SRAM中的每个存储单元包括两个驱动器MOS晶体管，两个传输门MOS晶体管和两个负载电阻。 MOS晶体管的栅极电极层由设置在半导体衬底的表面上的第一级导电层形成。 每个存储单元中的两个驱动器MOS晶体管的源极区域共同连接，并且通过第二级导电层进一步连接到地电位点。 每个存储单元中的两个负载电阻由第三级高电阻材料层形成。 第二级导电层由低电阻材料层形成。 因此，两个驱动器MOS晶体管的源极的电阻降低。

公开(公告)号：US4792841A

公开(公告)日：1988-12-20

申请号：US634037

申请日：1984-07-24

申请人： Kouichi Nagasawa ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Satoshi Meguro

发明人： Kouichi Nagasawa ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Satoshi Meguro

IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8244 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11 ,  H01L29/04

CPC分类号： H01L27/1112 ,  H01L21/28525 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/522 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S257/903

摘要： Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after the polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

摘要翻译： 公开了包括多个硅栅型MOSFET的MOSIC，其中在与多晶硅栅极同时形成多晶硅布线之后，与源极和漏极区域接触的电极由多晶硅制成，以便连接到多晶硅 从而防止源极和漏极区域的浅的pn结被触点破坏并提供与一个硅芯片的高度集成。

公开(公告)号：US4609835A

公开(公告)日：1986-09-02

申请号：US471130

申请日：1983-03-01

申请人： Yoshio Sakai ,  Toshiaki Masuhara ,  Osamu Minato ,  Toshio Sasaki

发明人： Yoshio Sakai ,  Toshiaki Masuhara ,  Osamu Minato ,  Toshio Sasaki

IPC分类号： G11C11/412 ,  H01L27/06 ,  H01L27/085 ,  H01L27/11 ,  G11C11/40 ,  H01L27/04 ,  H01L29/78 ,  H03K19/094

CPC分类号： H01L27/0688 ,  G11C11/412 ,  H01L27/085 ,  H01L27/1104 ,  H01L27/1112

摘要： Disclosed is a semiconductor integrated circuit which comprises an n-type silicon substrate, a p-type well region having an opening at a part thereof, which is formed on the surface portion of the substrate, an MOS transistor formed in the p-type region and a resistance layer extended from the drain region of the MOS transistor to the opening of the p-type well region through a insulating film formed on the surface of the substrate, in which the drain region of the MOS transistor is electrically connected to the silicon substrate through the resistance layer so that a current is supplied to the MOS transistor.

摘要翻译： 公开了一种半导体集成电路，其包括n型硅衬底，形成在衬底的表面部分上的具有开口的p型阱区，形成在p型区域中的MOS晶体管 以及电阻层，其通过形成在所述衬底的表面上的绝缘膜从所述MOS晶体管的漏极区延伸到所述p型阱区的开口，其中所述MOS晶体管的漏极区域与所述硅 衬底通过电阻层，以便向MOS晶体管提供电流。

公开(公告)号：US4377819A

公开(公告)日：1983-03-22

申请号：US032017

申请日：1979-04-20

申请人： Yoshio Sakai ,  Toshiaki Masuhara ,  Osamu Minato ,  Toshio Sasaki ,  Hisao Katto ,  Norikazu Hashimoto ,  Shin-ichi Muramatsu ,  Akihiro Tomozawa

发明人： Yoshio Sakai ,  Toshiaki Masuhara ,  Osamu Minato ,  Toshio Sasaki ,  Hisao Katto ,  Norikazu Hashimoto ,  Shin-ichi Muramatsu ,  Akihiro Tomozawa

IPC分类号： G11C11/412 ,  H01L21/02 ,  H01L21/318 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L27/11 ,  H01L29/06 ,  H01L29/40 ,  H01L29/41 ,  H01L29/04

CPC分类号： H01L29/402 ,  H01L21/3185 ,  H01L27/0605 ,  H01L27/1112 ,  H01L28/20 ,  H01L29/41

摘要： A semiconductor device including at least a resistance element formed of polycrystalline silicon having a high resistivity. An electrode is provided on the high resistance polycrystalline silicon region with a silicon dioxide film and a silicon nitride film being interposed therebetween. The electrode is coupled to the ground potential. In this manner, high stability is obtained in the behavior of the resistance element inasmuch as the formation of a parasitic MOS device under said high resistance region is suppressed, and the threshold voltage of any such MOS device is made raised.

摘要翻译： 一种半导体器件，至少包括由具有高电阻率的多晶硅形成的电阻元件。 在具有二氧化硅膜的高电阻多晶硅区域上设置电极，并且在其间插入有氮化硅膜。 电极与地电位耦合。 以这种方式，由于抑制了在所述高电阻区域下的寄生MOS器件的形成，所以电阻元件的性能得到了很高的稳定性，并且提高了任何这种MOS器件的阈值电压。

公开(公告)号：US5028975A

公开(公告)日：1991-07-02

申请号：US527641

申请日：1990-05-23

申请人： Kouichi Nagasawa ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Satoshi Meguro

发明人： Kouichi Nagasawa ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Satoshi Meguro

IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8244 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11

CPC分类号： H01L27/1112 ,  H01L21/28525 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/522 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S257/903

摘要： Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, the electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

公开(公告)号：US4492974A

公开(公告)日：1985-01-08

申请号：US350589

申请日：1982-02-22

申请人： Isao Yoshida ,  Takeaki Okabe ,  Mineo Katsueda ,  Minoru Nagata ,  Toshiaki Masuhara ,  Kazutoshi Ashikawa ,  Hideaki Kato ,  Mitsuo Ito ,  Shigeo Ohtaka ,  Osamu Minato ,  Yoshio Sakai

发明人： Isao Yoshida ,  Takeaki Okabe ,  Mineo Katsueda ,  Minoru Nagata ,  Toshiaki Masuhara ,  Kazutoshi Ashikawa ,  Hideaki Kato ,  Mitsuo Ito ,  Shigeo Ohtaka ,  Osamu Minato ,  Yoshio Sakai

IPC分类号： H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/78 ,  H01L29/861 ,  H01L29/90 ,  H02H3/20

CPC分类号： H01L29/7811 ,  H01L27/0255 ,  H01L27/0688 ,  H01L29/7808 ,  H01L29/861 ,  H01L2924/0002

摘要： A semiconductor integrated circuit device is provided to include a vertical type MOSFET and a gate protection element for the MOSFET. The vertical type MOSFET is made up of a silicon layer of n-type conductivity formed on an n.sup.+ -type silicon substrate, a base region of p-type conductivity formed in the surface of the silicon layer of n-type conductivity, an n.sup.+ -type source region provided in the base region, and a gate electrode formed on a portion of the base region through a gate insulating film. The silicon substrate serves as the drain. The gate protection element is formed of a polycrystalline silicon layer which is provided on the base region through an insulating film and includes at least one pn junction. By virtue of forming the gate protection element over the base region rather than directly over the substrate, a more stable operation is achieved.

摘要翻译： 提供半导体集成电路器件以包括用于MOSFET的垂直型MOSFET和栅极保护元件。 垂直型MOSFET由n +型硅衬底上形成的n型导电硅层，n型导电性硅层表面形成的p型导电基极区，n +型硅衬底， 设置在基极区域中的源极区，以及通过栅极绝缘膜形成在基极区域的一部分上的栅电极。 硅衬底用作漏极。 栅极保护元件由多晶硅层形成，该多晶硅层通过绝缘膜设置在基极区上并且包括至少一个pn结。 通过在基极区域而不是直接在衬底上形成栅极保护元件，实现更稳定的操作。