公开(公告)号：US09876080B2

公开(公告)日：2018-01-23

申请号：US15218922

申请日：2016-07-25

Applicant: IMEC VZW

Inventor： Bernardette Kunert ,  Robert Langer ,  Geert Eneman

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/423 ,  H01L29/04 ,  H01L21/324 ,  H01L21/306 ,  H01L29/161 ,  H01L29/775 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02469 ,  H01L21/02513 ,  H01L21/02524 ,  H01L21/02532 ,  H01L21/30612 ,  H01L21/3245 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/42356 ,  H01L29/775

Abstract: Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant. The semiconductor structure also includes (iv) one or more group IV monocrystalline structures abutting the buffer structure and that are made of a material having a second lattice constant, different from the first lattice constant.

公开(公告)号：US09406777B2

公开(公告)日：2016-08-02

申请号：US14667376

申请日：2015-03-24

Applicant: IMEC VZW ,  Samsung Electronics Co. Ltd.

Inventor： Seung Hun Lee ,  Geert Eneman

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/267

CPC classification number: H01L29/66545 ,  H01L21/3065 ,  H01L21/3083 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for manufacturing a transistor device comprising a channel layer is disclosed. In one example, the method includes providing a substrate, epitaxially growing a strained layer on the substrate (defect free), epitaxially growing the channel layer on the epitaxially grown strained layer, and providing a gate structure on the channel layer. In this example, the method also includes selectively etching into the channel layer and at least partially in the epitaxially grown strained layer, thereby using the gate structure as a mask, and thereby creating a protrusion extending from the substrate. The protrusion may comprise a portion of the channel layer and at least an upper portion of the epitaxially grown strained layer, and may allow for elastic relaxation in the portions.

Abstract translation: 公开了一种制造包括沟道层的晶体管器件的方法。 在一个实例中，该方法包括提供衬底，在衬底上外延生长应变层（无缺陷），外延生长外延生长的应变层上的沟道层，并在沟道层上提供栅极结构。 在该示例中，该方法还包括选择性地蚀刻到沟道层中并且至少部分地在外延生长的应变层中蚀刻，从而使用栅极结构作为掩模，从而产生从衬底延伸的突起。 突起可以包括沟道层的一部分和外延生长的应变层的至少上部，并且可以允许部分中的弹性松弛。

公开(公告)号：US09368498B2

公开(公告)日：2016-06-14

申请号：US14878012

申请日：2015-10-08

Applicant: IMEC VZW

Inventor： Geert Eneman ,  Benjamin Vincent ,  Voon Yew Thean

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7849

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

公开(公告)号：US09257539B2

公开(公告)日：2016-02-09

申请号：US14566073

申请日：2014-12-10

Applicant: IMEC VZW

Inventor： Rita Rooyackers ,  Nadine Collaert ,  Geert Eneman

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/20 ,  H01L21/36 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/6681 ,  G10L2015/223 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.

Abstract translation: 提供了一种用于制造晶体管器件的方法，包括在衬底上提供多个平行的纳米线; 在所述平行纳米线的中心部分上提供虚拟栅极结构; 外延生长第二材料的延伸部分，选择性地在平行的纳米线上，在中心部分之外; 在所述虚拟栅极结构和所述延伸部分周围和顶部设置填充层; 去除伪栅极结构以产生栅极沟槽，暴露平行纳米线的中心部分; 在所述栅极沟槽的侧壁上提供间隔结构，以限定最终的栅极沟槽; 使平行的纳米线变薄，从而在纳米线和间隔物结构之间产生自由空间; 并且在所述平行的纳米线上或周围选择性地生长量子阱层，至少部分地填充所述自由空间，从而提供所述量子阱层和延伸部分之间的连接。

公开(公告)号：US20150179755A1

公开(公告)日：2015-06-25

申请号：US14566073

申请日：2014-12-10

Applicant: IMEC VZW

Inventor： Rita Rooyackers ,  Nadine Collaert ,  Geert Eneman

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/6681 ,  G10L2015/223 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.

Abstract translation: 提供了一种用于制造晶体管器件的方法，包括在衬底上提供多个平行的纳米线; 在所述平行纳米线的中心部分上提供虚拟栅极结构; 外延生长第二材料的延伸部分，选择性地在平行的纳米线上，在中心部分之外; 在所述虚拟栅极结构和所述延伸部分周围和顶部设置填充层; 去除伪栅极结构以产生栅极沟槽，暴露平行纳米线的中心部分; 在所述栅极沟槽的侧壁上提供间隔结构，以限定最终的栅极沟槽; 使平行的纳米线变薄，从而在纳米线和间隔物结构之间产生自由空间; 并且在所述平行的纳米线上或周围选择性地生长量子阱层，至少部分地填充所述自由空间，从而提供所述量子阱层和延伸部分之间的连接。

公开(公告)号：US20130154112A1

公开(公告)日：2013-06-20

申请号：US13713932

申请日：2012-12-13

Applicant: IMEC ,  Katholieke Universiteit Leuven, K.U. Leuven R&D

Inventor： Wenqi Zhang ,  Wei-E Wang ,  Geert Eneman ,  Eric Beyne ,  Andrej Ivankovic

IPC: H01L21/48 ,  H01L21/18 ,  H01L23/538

CPC classification number: H01L21/4853 ,  H01L21/185 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/02235 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05546 ,  H01L2224/05562 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/14181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The disclosure is related to a substrate suitable for use in a stack of interconnected substrates, comprising: a base layer having a front side and a back side surface parallel to the plane of the base layer; one or more interconnect structures, each of said structures comprising: a via filled with an electrically conductive material, said via running through the complete thickness of the base layer, thereby forming an electrical connection between said front side and back side surfaces of the base layer, and on the back side surface of the base layer: a landing pad and a micro-bump in electrical connection with said filled via; characterized in that the backside surface of said base layer comprises one or more isolation ring trenches each of said trenches surrounding one or more of said interconnect structures. The disclosure is equally related to methods for producing said substrates and stacks of substrates.

Abstract translation: 本公开涉及适用于互连基板堆叠的基板，包括：基底层，其具有平行于基底层的平面的前侧和后侧表面; 一个或多个互连结构，每个所述结构包括：填充有导电材料的通孔，所述通孔穿过基底层的整个厚度，由此在基底层的所述前侧和后侧表面之间形成电连接 并且在所述基底层的背侧表面上：与所述填充的通孔电连接的着陆垫和微凸起; 其特征在于，所述基底层的背面包括一个或多个隔离环沟槽，每个所述沟槽围绕一个或多个所述互连结构。 本公开内容同样涉及用于生产所述衬底和衬底叠层的方法。

公开(公告)号：US11387350B2

公开(公告)日：2022-07-12

申请号：US16719852

申请日：2019-12-18

Applicant: IMEC vzw

Inventor： Geert Eneman ,  Bartlomiej Pawlak ,  Liesbeth Witters ,  Geoffrey Pourtois

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/161 ,  H01L29/78

Abstract: According to one aspect, a method of fabricating a semiconductor structure includes cutting a semiconductor fin extending along a substrate. Cutting the semiconductor fin can comprise forming a fin cut mask. The fin cut mask can define a number of masked regions and a number of cut regions. The method can include cutting the fin into a number of fin parts by etching the fin in the cut regions. The method can further comprise forming an epitaxial semiconductor capping layer on the fin prior to forming the fin cut mask or on the fin parts subsequent to cutting the fin. A capping layer material and a fin material can be lattice mismatched. According to another aspect, a corresponding semiconductor structure comprises fin parts.

公开(公告)号：US20200083116A1

公开(公告)日：2020-03-12

申请号：US16567485

申请日：2019-09-11

Applicant: IMEC VZW

Inventor： Steven Demuynck ,  Geert Eneman ,  Vladimir Machkaoutsan

IPC: H01L21/8238 ,  H01L27/11 ,  H01L27/092 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66

Abstract: A method of forming gate contacts and/or contact lines on a plurality of fins. The method comprises providing a wafer comprising a semiconductor structure which comprises a plurality of fins. The method further comprises patterning at least one continuous trench over the fins, and filling at least one of the trenches with metal to obtain at least one continuous gate in contact with the fins and/or filling at least one of the trenches with metal to obtain at least one continuous contact line in contact with the fins. The method further comprises cutting the metal of the at least one gate and/or cutting the metal of the at least one contact line in between some of the fins.

公开(公告)号：US20190172913A1

公开(公告)日：2019-06-06

申请号：US16171627

申请日：2018-10-26

Applicant: IMEC VZW

Inventor： Hu Liang ,  Xiuju Zhou ,  Geert Eneman

IPC: H01L29/20 ,  H01L29/778 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L33/32 ,  H01L33/00 ,  H01L29/04 ,  H01L21/02

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a monocrystalline substrate having an upper surface covered with a masking layer comprising at least one opening exposing the upper surface; filling the opening by epitaxially growing therein a first layer comprising a first Group III-nitride compound; and growing the first layer further above the opening and on the masking layer by epitaxial lateral overgrowth, wherein the at least one opening has a top surface defined by three or more straight edges forming a polygon parallel to the upper surface and oriented in such a way with respect to the crystal lattice of the monocrystalline substrate so as to permit the epitaxial lateral overgrowth of the first layer in a direction perpendicular to at least one of the edges, thereby forming the semiconductor structure as an elongated structure.

公开(公告)号：US09698262B2

公开(公告)日：2017-07-04

申请号：US15072130

申请日：2016-03-16

Applicant: IMEC VZW ,  GLOBALFOUNDRIES INC.

Inventor： Bartlomiej Pawlak ,  Geert Eneman

IPC: H01L29/74 ,  H01L29/80 ,  H01L29/94 ,  H01L21/00 ,  H01L21/338 ,  H01L21/337 ,  H01L29/78 ,  H01L21/765 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L21/76 ,  H01L21/765 ,  H01L29/0607 ,  H01L29/0657 ,  H01L29/1083 ,  H01L29/42356

Abstract: A vertical FinFET semiconductor device and a method of forming the same are disclosed. In one aspect, the semiconductor device includes a current-blocking structure formed over a semiconductor structure and a semiconductor fin formed on the current-blocking structure. The current blocking structure includes a first layer of a first conductive type, a layer of a second conductive type over the first layer, and a second layer of the first conductive type over the layer of the second conductive type. The semiconductor fin has a doped bottom portion contacting the current-blocking structure, a doped top portion formed vertically opposite to the doped bottom portion and a channel portion vertically interposed between the doped bottom portion and the doped top portion.