公开(公告)号：US20190244862A1

公开(公告)日：2019-08-08

申请号：US16271626

申请日：2019-02-08

Applicant: IMEC vzw

Inventor： Bernardette Kunert ,  Niamh Waldron ,  Weiming Guo

IPC: H01L21/8258 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/8252 ,  H01L29/786

CPC classification number: H01L21/8258 ,  H01L21/823487 ,  H01L21/8252 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface. The semiconductor device further includes a first vertical channel layer laterally interposed between and in contact with the dielectric layer and the dielectric filling layer at a first side of the dielectric filling layer, wherein the first vertical channel layer extends above the common top surface.

公开(公告)号：US20190219846A1

公开(公告)日：2019-07-18

申请号：US16228486

申请日：2018-12-20

Applicant: IMEC vzw

Inventor： Joris Van Campenhout ,  Ashwyn Srinivasan ,  Bernardette Kunert ,  Maria loanna Pantouvaki

IPC: G02F1/017

CPC classification number: G02F1/01708 ,  G02B6/131 ,  G02B2006/12097 ,  G02B2006/12128 ,  G02B2006/12178 ,  G02F1/025 ,  G02F1/225 ,  G02F2001/01791

Abstract: A III-V semiconductor waveguide nanoridge structure having a narrow supporting base with a freestanding wider body portion on top, is disclosed. In one aspect, the III-V waveguide includes a PIN diode. The waveguide comprises a III-V semiconductor waveguide core formed in the freestanding wider body portion; at least one heterojunction incorporated in the III-V semiconductor waveguide core; a bottom doped region of a first polarity positioned at a bottom of the narrow supporting base, forming a lower contact; and an upper doped region of a second polarity, forming an upper contact. The upper contact is positioned in at least one side wall of the freestanding wider body portion.

公开(公告)号：US10224250B2

公开(公告)日：2019-03-05

申请号：US15713417

申请日：2017-09-22

Applicant: IMEC VZW

Inventor： Bernardette Kunert ,  Niamh Waldron ,  Weiming Guo

IPC: H01L21/8258 ,  H01L21/8234 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface. The semiconductor device further includes a first vertical channel layer laterally interposed between and in contact with the dielectric layer and the dielectric filling layer at a first side of the dielectric filling layer, wherein the first vertical channel layer extends above the common top surface.

公开(公告)号：US20250151312A1

公开(公告)日：2025-05-08

申请号：US18934774

申请日：2024-11-01

Applicant: IMEC VZW

Inventor： Sachin Yadav ,  Bernardette Kunert ,  Bjorn Vermeersch ,  Bertrand Parvais ,  Abhitosh Vais ,  Guillaume Boccardi ,  Annie Kumar

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/737

Abstract: Example embodiments relate to semiconductor processing methods and semiconductor components obtainable by applying the semiconductor processing methods. One example method includes providing a substrate formed of a first semiconductor material. The method also includes providing a mesa structure on the substrate and in direct contact with the substrate. The mesa structure is isolated on all lateral sides by dielectric material. Active layers of a semiconductor device are integrated in an upper portion of the mesa structure. Additionally, the method includes producing one or more openings through the dielectric material. Further, the method includes forming a cavity by removing a bottom portion of the mesa structure through the one or more openings or removing the dielectric material in a region directly adjacent to the bottom portion of the mesa structure. In addition, the method includes obtaining a thermally conductive volume by filling the cavity with a material of high thermal conductivity.

公开(公告)号：US20180082901A1

公开(公告)日：2018-03-22

申请号：US15713417

申请日：2017-09-22

Applicant: IMEC VZW

Inventor： Bernardette Kunert ,  Niamh Waldron ,  Weiming Guo

IPC: H01L21/8258 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8252 ,  H01L21/8234

CPC classification number: H01L21/8258 ,  H01L21/823487 ,  H01L21/8252 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface. The semiconductor device further includes a first vertical channel layer laterally interposed between and in contact with the dielectric layer and the dielectric filling layer at a first side of the dielectric filling layer, wherein the first vertical channel layer extends above the common top surface.

公开(公告)号：US20180061712A1

公开(公告)日：2018-03-01

申请号：US15687304

申请日：2017-08-25

Applicant: IMEC VZW

Inventor： Yves Mols ,  Niamh Waldron ,  Bernardette Kunert

IPC: H01L21/78 ,  H01L21/683

CPC classification number: H01L21/7813 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/7806 ,  H01L21/8252 ,  H01L21/8258

Abstract: The disclosed technology generally relates to manufacturing of semiconductor devices, and more particularly to manufacturing of a semiconductor device by transferring an active layer from a donor substrate. One aspect is a method of manufacturing a semiconductor device includes providing a donor wafer for transferring an active layer, comprising a group IV, a group III-IV or a group II-VI semiconductor material, to a handling wafer. The method includes forming the active layer on a sacrificial layer of the donor wafer, bonding the donor wafer to the handling wafer, and selectively etching the sacrificial layer to remove the donor wafer from the handling wafer, thereby leaving the active layer on the handling wafer.

公开(公告)号：US09876080B2

公开(公告)日：2018-01-23

申请号：US15218922

申请日：2016-07-25

Applicant: IMEC VZW

Inventor： Bernardette Kunert ,  Robert Langer ,  Geert Eneman

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/423 ,  H01L29/04 ,  H01L21/324 ,  H01L21/306 ,  H01L29/161 ,  H01L29/775 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02469 ,  H01L21/02513 ,  H01L21/02524 ,  H01L21/02532 ,  H01L21/30612 ,  H01L21/3245 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/42356 ,  H01L29/775

Abstract: Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant. The semiconductor structure also includes (iv) one or more group IV monocrystalline structures abutting the buffer structure and that are made of a material having a second lattice constant, different from the first lattice constant.

公开(公告)号：US20170054021A1

公开(公告)日：2017-02-23

申请号：US15208783

申请日：2016-07-13

Applicant: IMEC VZW

Inventor： Bernardette Kunert ,  Robert Langer

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/04 ,  H01L29/205

CPC classification number: H01L29/7846 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/785

Abstract: The present disclosure relates to a semiconductor structure and a method of preparation including a silicon monocrystalline substrate, and a III-V structure abutting the silicon monocrystalline substrate. The semiconductor structure includes an InaGabAs structure overlaying the III-V structure, where a is from 0.40 to 1, b from 0 to 0.60, and a+b equal to 1.00. The III-V structure has a top surface facing away from the silicon substrate. The top surface is GagXxPpSbsZz, where X includes one or more group III elements other than Ga and Z is one or more group V elements other than P or Sb. g is from 0.80 to 1.00, x is from 0 to 0.20, z is from 0 to 0.30, p is from 0.10 to 0.55, and s is from 0.50 to 0.80, g+x is equal to 1.00 and p+s+z is equal to 1.00.

Abstract translation: 本公开涉及一种半导体结构和包括硅单晶衬底的制备方法以及邻接硅单晶衬底的III-V结构。 半导体结构包括覆盖III-V结构的InaGabAs结构，其中a为0.40至1，b为0至0.60，a + b等于1.00。 III-V结构具有背离硅衬底的顶表面。 上表面是GagXxPpSbsZz，其中X包括除Ga之外的一个或多个III族元素，Z是除P或Sb以外的一种或多种V族元素。 g为0.80〜1.00，x为0〜0.20，z为0〜0.30，p为0.10〜0.55，s为0.50〜0.80，g + x为1.00，p + s + z为 等于1.00。

公开(公告)号：US20230395561A1

公开(公告)日：2023-12-07

申请号：US18328182

申请日：2023-06-02

Applicant: IMEC VZW

Inventor： Abhitosh Vais ,  Bertrand Paravais ,  Guillaume Boccardi ,  Bernardette Kunert ,  Yves Mols ,  Sachin Yadav

IPC: H01L23/00 ,  H01L29/778 ,  H01L29/737 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L24/80 ,  H01L29/778 ,  H01L29/737 ,  H01L21/76898 ,  H01L21/78 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: The present disclosure relates to at least one multilayer structure that is produced on a semiconductor donor wafer, by growing e.g. group III-V material in a cavity formed in a dielectric support layer. A template layer embeds the multilayer structure. The multilayer structure comprises a release layer that is accessible from the sides. The method further comprises the production of a device and the production of conductive paths connected to the device and terminating in a number of contact pads which are coplanar with a first dielectric bonding surface. The donor wafer is then bonded to a carrier wafer. TSV openings are then produced from the back side of the carrier wafer and an etchant is provided for selectively removing layers of the multilayer structure. The etchant is supplied through the TSV openings for the removal of the release layer. The donor wafer is thereby released to form separate semiconductor chips.

公开(公告)号：US11646200B2

公开(公告)日：2023-05-09

申请号：US17323540

申请日：2021-05-18

Applicant: IMEC VZW

Inventor： Liesbeth Witters ,  Niamh Waldron ,  Amey Mahadev Walke ,  Bernardette Kunert ,  Yves Mols

IPC: H01L21/02 ,  H01L29/267 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/02395 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02398 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7787

Abstract: A method for forming a III-V construction over a group IV substrate comprises providing an assembly comprising the group IV substrate and a dielectric thereon. The dielectric layer comprises a trench exposing the group IV substrate. The method further comprises initiating growth of a first III-V structure in the trench, continuing growth out of the trench on top of the bottom part, growing epitaxially a sacrificial second III-V structure on the top part of the first III-V structure, and growing epitaxially a third III-V structure on the sacrificial second III-V structure. The third III-V structure comprises a top III-V layer. The method further comprises physically disconnecting a first part of the top layer from a second part thereof, and contacting the sacrificial second III-V structure with the liquid etching medium.