公开(公告)号：US11322390B2

公开(公告)日：2022-05-03

申请号：US16844845

申请日：2020-04-09

Applicant: IMEC vzw

Inventor： Amey Mahadev Walke ,  Niamh Waldron ,  Nadine Collaert ,  Ming Zhao

IPC: H01L25/16 ,  H01L21/762 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423

Abstract: The disclosed technology relates generally to the field of semiconductor devices, and more particularly to co-integration of GaN-based devices with Si-based devices. In one aspect, a method of forming a semiconductor device includes forming a first wafer including, on a front side thereof, a III-V semiconductor layer stack formed on a first substrate and a first bonding layer. The III-V semiconductor layer stack includes a GaN-based device layer structure formed on the first substrate. The method additionally includes, subsequent to forming the first wafer, bonding the first bonding layer to a second bonding layer of a second wafer. The second wafer includes a second silicon substrate supporting an active device layer, a back-end-of-line interconnect structure and the second bonding layer. The method further comprises, subsequent to bonding, thinning the first wafer from a backside, wherein thinning includes removing at least the first substrate. In another aspect, a semiconductor device includes a cointegrated N-polar HEMT.

公开(公告)号：US20180082901A1

公开(公告)日：2018-03-22

申请号：US15713417

申请日：2017-09-22

Applicant: IMEC VZW

Inventor： Bernardette Kunert ,  Niamh Waldron ,  Weiming Guo

IPC: H01L21/8258 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8252 ,  H01L21/8234

CPC classification number: H01L21/8258 ,  H01L21/823487 ,  H01L21/8252 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface. The semiconductor device further includes a first vertical channel layer laterally interposed between and in contact with the dielectric layer and the dielectric filling layer at a first side of the dielectric filling layer, wherein the first vertical channel layer extends above the common top surface.

公开(公告)号：US20180061712A1

公开(公告)日：2018-03-01

申请号：US15687304

申请日：2017-08-25

Applicant: IMEC VZW

Inventor： Yves Mols ,  Niamh Waldron ,  Bernardette Kunert

IPC: H01L21/78 ,  H01L21/683

CPC classification number: H01L21/7813 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/7806 ,  H01L21/8252 ,  H01L21/8258

Abstract: The disclosed technology generally relates to manufacturing of semiconductor devices, and more particularly to manufacturing of a semiconductor device by transferring an active layer from a donor substrate. One aspect is a method of manufacturing a semiconductor device includes providing a donor wafer for transferring an active layer, comprising a group IV, a group III-IV or a group II-VI semiconductor material, to a handling wafer. The method includes forming the active layer on a sacrificial layer of the donor wafer, bonding the donor wafer to the handling wafer, and selectively etching the sacrificial layer to remove the donor wafer from the handling wafer, thereby leaving the active layer on the handling wafer.

公开(公告)号：US09601488B2

公开(公告)日：2017-03-21

申请号：US15138056

申请日：2016-04-25

Applicant: IMEC VZW

Inventor： Niamh Waldron ,  Clement Merckling ,  Nadine Collaert

IPC: H01L29/41 ,  H01L27/088 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/04 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L21/02

CPC classification number: H01L27/0886 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02538 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/401 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.

公开(公告)号：US20160240532A1

公开(公告)日：2016-08-18

申请号：US15138056

申请日：2016-04-25

Applicant: IMEC VZW

Inventor： Niamh Waldron ,  Clement Merckling ,  Nadine Collaert

IPC: H01L27/088 ,  H01L29/20 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/0886 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02538 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/401 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.

公开(公告)号：US09324818B2

公开(公告)日：2016-04-26

申请号：US14671134

申请日：2015-03-27

Applicant: IMEC VZW

Inventor： Niamh Waldron ,  Clement Merckling ,  Nadine Collaert

IPC: H01L29/41 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/04 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/0886 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02538 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/401 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及栅极全能半导体器件及其制造方法。 一方面，该方法包括在STI区域之间的半导体衬底上提供由源区域和漏极区域锚定的至少一个悬浮纳米结构。 悬浮的纳米结构由与半导体衬底的结晶半导体材料不同的结晶半导体材料形成。 一个栅极叠层围绕至少一个悬浮的纳米结构。

公开(公告)号：US11195767B2

公开(公告)日：2021-12-07

申请号：US16550085

申请日：2019-08-23

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Liesbeth Witters ,  Niamh Waldron ,  Robert Langer ,  Bernardette Kunert

IPC: H01L21/8258 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/3065 ,  H01L29/423 ,  H01L21/308

Abstract: A method for forming a semiconductor structure comprising: providing a silicon substrate having a first and a second flat top surface belonging to a first and a second substrate region respectively, the first top surface being lower than the second top surface, thereby forming a step delimiting the first and the second substrate region. The method further comprises forming, at least partially, one or more silicon semiconductor devices in the second substrate region, and forming, at least partially, one or more III-V semiconductor devices in the first substrate region.

公开(公告)号：US20200075750A1

公开(公告)日：2020-03-05

申请号：US16552468

申请日：2019-08-27

Applicant: IMEC vzw

Inventor： Robert Langer ,  Niamh Waldron ,  Bernardette Kunert

IPC: H01L29/737 ,  H01L27/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L21/02

Abstract: The disclosed technology generally relates to integrated circuit devices having at least one transistor, and methods of fabricating the same. In one aspect, an integrated circuit device can be produced from a silicon substrate and can include at least one nano-ridge transistor formed from III-V semiconducting crystal portions. The III-V portions can be grown epitaxially from the silicon substrate using an intermediate portion which can be adapted to produce aspect ratio trapping. The nano-ridge transistor can have a reduced footprint on the silicon substrate, may be adapted for power RF applications, and can be combined with MOS or CMOS transistors within one and a same integrated circuit.

公开(公告)号：US20190244862A1

公开(公告)日：2019-08-08

申请号：US16271626

申请日：2019-02-08

Applicant: IMEC vzw

Inventor： Bernardette Kunert ,  Niamh Waldron ,  Weiming Guo

IPC: H01L21/8258 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/8252 ,  H01L29/786

CPC classification number: H01L21/8258 ,  H01L21/823487 ,  H01L21/8252 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface. The semiconductor device further includes a first vertical channel layer laterally interposed between and in contact with the dielectric layer and the dielectric filling layer at a first side of the dielectric filling layer, wherein the first vertical channel layer extends above the common top surface.

公开(公告)号：US10224250B2

公开(公告)日：2019-03-05

申请号：US15713417

申请日：2017-09-22

Applicant: IMEC VZW

Inventor： Bernardette Kunert ,  Niamh Waldron ,  Weiming Guo

IPC: H01L21/8258 ,  H01L21/8234 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface. The semiconductor device further includes a first vertical channel layer laterally interposed between and in contact with the dielectric layer and the dielectric filling layer at a first side of the dielectric filling layer, wherein the first vertical channel layer extends above the common top surface.