公开(公告)号：US11424201B2

公开(公告)日：2022-08-23

申请号：US16012341

申请日：2018-06-19

Applicant: Infineon Technologies AG

Inventor： Michael Rogalli ,  Johann Gatterbauer ,  Wolfgang Lehnert ,  Kurt Matoy ,  Evelyn Napetschnig ,  Manfred Schneegans ,  Bernhard Weidgans

IPC: H01L23/00

Abstract: A method of forming an aluminum oxide layer is provided. The method includes providing a metal surface including at least one metal of a group of metals, the group of metals consisting of copper, aluminum, palladium, nickel, silver, and alloys thereof. The method further includes depositing an aluminum oxide layer on the metal surface by atomic layer deposition, wherein a maximum processing temperature during the depositing is 280° C., such that the aluminum oxide layer is formed with a surface having a liquid solder contact angle of less than 40°.

公开(公告)号：US20220059477A1

公开(公告)日：2022-02-24

申请号：US17400303

申请日：2021-08-12

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Jens Brandenburg ,  Christoffer Erbert ,  Joachim Hirschler ,  Oliver Humbel ,  Thomas Rupp ,  Carsten Schaeffer ,  Julia Zischang

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/485

Abstract: A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

公开(公告)号：US10573611B2

公开(公告)日：2020-02-25

申请号：US16163006

申请日：2018-10-17

Applicant: Infineon Technologies AG

Inventor： Kamil Karlovsky ,  Evelyn Napetschnig ,  Michael Ehmann ,  Mark James Harrison ,  Anton Pugatschow

IPC: H01L23/00 ,  H01L21/683

Abstract: A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.

公开(公告)号：US20190051624A1

公开(公告)日：2019-02-14

申请号：US16163006

申请日：2018-10-17

Applicant: Infineon Technologies AG

Inventor： Kamil Karlovsky ,  Evelyn Napetschnig ,  Michael Ehmann ,  Mark James Harrison ,  Anton Pugatschow

IPC: H01L23/00

Abstract: A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.

公开(公告)号：US20180366427A1

公开(公告)日：2018-12-20

申请号：US16012341

申请日：2018-06-19

Applicant: Infineon Technologies AG

Inventor： Michael Rogalli ,  Johann Gatterbauer ,  Wolfgang Lehnert ,  Kurt Matoy ,  Evelyn Napetschnig ,  Manfred Schneegans ,  Bernhard Weidgans

IPC: H01L23/00

Abstract: A method of forming an aluminum oxide layer is provided. The method includes providing a metal surface including at least one metal of a group of metals, the group of metals consisting of copper, aluminum, palladium, nickel, silver, and alloys thereof. The method further includes depositing an aluminum oxide layer on the metal surface by atomic layer deposition, wherein a maximum processing temperature during the depositing is 280° C., such that the aluminum oxide layer is formed with a surface having a liquid solder contact angle of less than 40°.

公开(公告)号：US20150123264A1

公开(公告)日：2015-05-07

申请号：US14070334

申请日：2013-11-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Evelyn Napetschnig ,  Ulrike Fastner ,  Alexander Heinrich ,  Thomas Fischer

IPC: H01L23/00 ,  H01L21/78

CPC classification number: H01L24/05 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3086 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/94 ,  H01L24/96 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02205 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05005 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05554 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/10126 ,  H01L2224/11009 ,  H01L2224/11011 ,  H01L2224/11019 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11845 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/26125 ,  H01L2224/27009 ,  H01L2224/27019 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/27845 ,  H01L2224/29007 ,  H01L2224/29013 ,  H01L2224/291 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/206 ,  H01L2924/2064 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01032 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/27

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

Abstract translation: 根据本发明的实施例，形成半导体器件的方法包括在衬底的第一主表面上形成接触层。 衬底包括由切口区域分隔开的器件区域。 接触层设置在切口区域和器件区域中。 在器件区域上形成结构化的焊料层。 在形成结构化的焊料层之后，在切割区域处露出接触层。 切割区域中的接触层和基底。

公开(公告)号：US08866299B2

公开(公告)日：2014-10-21

申请号：US13932851

申请日：2013-07-01

Applicant: Infineon Technologies AG

Inventor： Mark Harrison ,  Evelyn Napetschnig ,  Franz Stueckler

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/683

CPC classification number: H01L21/3065 ,  H01L21/02057 ,  H01L21/6836 ,  H01L24/03 ,  H01L24/05 ,  H01L2221/68327 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05005 ,  H01L2224/05083 ,  H01L2224/05099 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05541 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/047 ,  H01L2924/00

Abstract: A semiconductor device includes a workpiece having a bottom surface opposite the top surface. Metallization layers are disposed over the top surface and a protective layer is disposed over the metallization layers. The semiconductor device further includes a metal silicide layer disposed on the bottom surface. The metal silicide layer is less than about five atomic layers in thickness. A first metal layer is disposed over the metal silicide layer such that a metal of the first metal layer is the same as a metal of the metal silicide layer.

Abstract translation: 半导体器件包括具有与顶表面相对的底表面的工件。 金属化层设置在顶表面上方，并且保护层设置在金属化层上。 半导体器件还包括设置在底表面上的金属硅化物层。 金属硅化物层的厚度小于约5个原子层。 第一金属层设置在金属硅化物层上方，使得第一金属层的金属与金属硅化物层的金属相同。

公开(公告)号：US11735534B2

公开(公告)日：2023-08-22

申请号：US17333186

申请日：2021-05-28

Applicant: Infineon Technologies AG

Inventor： Harry Walter Sax ,  Johann Gatterbauer ,  Wolfgang Lehnert ,  Evelyn Napetschnig ,  Michael Rogalli

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/564 ,  H01L21/56 ,  H01L23/3142 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0382 ,  H01L2224/05687 ,  H01L2924/365

Abstract: A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.

公开(公告)号：US11615963B2

公开(公告)日：2023-03-28

申请号：US16926162

申请日：2020-07-10

Applicant: Infineon Technologies AG

Inventor： Paul Frank ,  Gretchen Adema ,  Thomas Bertaud ,  Michael Ehmann ,  Eric Graetz ,  Kamil Karlovsky ,  Evelyn Napetschnig ,  Werner Robl ,  Tobias Schmidt ,  Joachim Seifert ,  Frank Wagner ,  Stefan Woehlert

IPC: H01L23/00 ,  H01L21/285 ,  H01L29/861

Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.

公开(公告)号：US11367654B2

公开(公告)日：2022-06-21

申请号：US16248255

申请日：2019-01-15

Applicant: Infineon Technologies AG

Inventor： Karl Mayer ,  Evelyn Napetschnig ,  Michael Pinczolits ,  Michael Sternad ,  Michael Roesner

IPC: H01L21/78 ,  H01L23/544 ,  H01L23/48 ,  H01L23/58 ,  H01L23/00 ,  H01L23/31

Abstract: A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.