公开(公告)号：US10914018B2

公开(公告)日：2021-02-09

申请号：US16351116

申请日：2019-03-12

Applicant: Infineon Technologies AG

Inventor： Norbert Pielmeier ,  Chin Yung Lai ,  Swee Kah Lee ,  Muhammad Muhammat Sanusi ,  Evelyn Napetschnig ,  Nurfarena Othman ,  Siew Ching Seah

IPC: C25D7/12 ,  H01L23/495 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  C25D3/38

Abstract: A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallized surface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a thermal conductivity in a range of 340 to 400 W/mK and an electrical conductivity in a range of 80 to 110% IACS. One or more of the surfaces which comprise Cu and have a thermal conductivity in the range of 340 to 400 W/mK and an electrical conductivity in the range of 80 to 110% IACS also includes micropores having a diameter in a range of 1 μm to 10 μm. A method of manufacturing a metal surface with such micropores also is described.

公开(公告)号：US10262959B2

公开(公告)日：2019-04-16

申请号：US15295631

申请日：2016-10-17

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Ulrike Fastner ,  Alexander Heinrich ,  Thomas Fischer

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/308 ,  H01L21/683 ,  H01L21/268 ,  H01L21/304 ,  H01L23/31

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

公开(公告)号：US20250157857A1

公开(公告)日：2025-05-15

申请号：US19020532

申请日：2025-01-14

Applicant: Infineon Technologies AG

Inventor： Karl Mayer ,  Evelyn Napetschnig ,  Michael Pinczolits ,  Michael Sternad ,  Michael Roesner

IPC: H01L21/78 ,  H01L23/00 ,  H01L23/31

Abstract: In an embodiment a packaged semiconductor device includes a carrier, a component disposed on the carrier, the component having a substrate with a thickness of about 40 μm or less and a metal block, a single titanium layer connecting the component and the metal block, the single titanium layer functioning as a combined metal adhesion layer and a metal barrier layer, a connection layer connecting the carrier and the component, a conductive wire connecting a component contact pad of the component with a carrier contact pad of the carrier and an encapsulant encapsulating the component.

公开(公告)号：US20220246475A1

公开(公告)日：2022-08-04

申请号：US17660150

申请日：2022-04-21

Applicant: Infineon Technologies AG

Inventor： Karl Mayer ,  Evelyn Napetschnig ,  Michael Pinczolits ,  Michael Sternad ,  Michael Roesner

IPC: H01L21/78 ,  H01L23/00

Abstract: A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.

公开(公告)号：US20220216173A1

公开(公告)日：2022-07-07

申请号：US17376372

申请日：2021-07-15

Applicant: Infineon Technologies AG

Inventor： Thomas Behrens ,  Alexander Heinrich ,  Evelyn Napetschnig ,  Bernhard Weidgans ,  Catharina Wille ,  Christina Yeong

IPC: H01L23/00 ,  B23K35/26 ,  C22C13/02

Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.

公开(公告)号：US11069644B2

公开(公告)日：2021-07-20

申请号：US16556823

申请日：2019-08-30

Applicant: Infineon Technologies AG

Inventor： Thomas Behrens ,  Alexander Heinrich ,  Evelyn Napetschnig ,  Bernhard Weidgans ,  Catharina Wille ,  Christina Yeong

IPC: H01L23/00 ,  B23K35/26 ,  C22C13/02

Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.

公开(公告)号：US20200343094A1

公开(公告)日：2020-10-29

申请号：US16926162

申请日：2020-07-10

Applicant: Infineon Technologies AG

Inventor： Paul Frank ,  Gretchen Adema ,  Thomas Bertaud ,  Michael Ehmann ,  Eric Graetz ,  Kamil Karlovsky ,  Evelyn Napetschnig ,  Werner Robl ,  Tobias Schmidt ,  Joachim Seifert ,  Frank Wagner ,  Stefan Woehlert

IPC: H01L21/285 ,  H01L23/00 ,  H01L29/861

Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.

公开(公告)号：US09627335B2

公开(公告)日：2017-04-18

申请号：US14272535

申请日：2014-05-08

Applicant: Infineon Technologies AG

Inventor： Stephan Henneck ,  Evelyn Napetschnig ,  Daniel Pedone ,  Bernhard Weidgans ,  Simon Faiss ,  Ivan Nikitin

IPC: H01L21/4763 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/03424 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/03472 ,  H01L2224/03614 ,  H01L2224/05007 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05558 ,  H01L2224/05583 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2924/01023

Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization layer over a semiconductor workpiece; patterning the first metallization layer; and depositing a second metallization layer over the patterned first metallization layer, wherein depositing the second metallization layer includes an electroless deposition process including immersing the patterned first metallization layer in a metal electrolyte.

公开(公告)号：US20170033066A1

公开(公告)日：2017-02-02

申请号：US15295631

申请日：2016-10-17

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Ulrike Fastner ,  Alexander Heinrich ,  Thomas Fischer

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/268 ,  H01L23/31 ,  H01L21/78

CPC classification number: H01L24/05 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3086 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/94 ,  H01L24/96 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02205 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05005 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05554 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/10126 ,  H01L2224/11009 ,  H01L2224/11011 ,  H01L2224/11019 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11845 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/26125 ,  H01L2224/27009 ,  H01L2224/27019 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/27845 ,  H01L2224/29007 ,  H01L2224/29013 ,  H01L2224/291 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/206 ,  H01L2924/2064 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01032 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/27

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

Abstract translation: 根据本发明的实施例，形成半导体器件的方法包括在衬底的第一主表面上形成接触层。 衬底包括由切口区域分隔开的器件区域。 接触层设置在切口区域和器件区域中。 在器件区域上形成结构化的焊料层。 在形成结构化的焊料层之后，在切割区域处露出接触层。 切割区域中的接触层和基底。

公开(公告)号：US20230395539A1

公开(公告)日：2023-12-07

申请号：US18235585

申请日：2023-08-18

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Jens Brandenburg ,  Christoffer Erbert ,  Joachim Hirschler ,  Oliver Humbel ,  Thomas Rupp ,  Carsten Schaeffer ,  Julia Zischang

IPC: H01L23/00 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L23/485 ,  H01L23/53219 ,  H01L23/53233

Abstract: A method of manufacturing a semiconductor device includes forming a wiring metal layer structure; forming a dielectric layer structure arranged directly on the wiring metal layer structure; and forming a bonding pad metal layer structure arranged, at least partially, directly on the dielectric layer structure, wherein a layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure, wherein the wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.