公开(公告)号：USD801334S1

公开(公告)日：2017-10-31

申请号：US29505659

申请日：2015-12-26

Applicant: Intel Corporation

Designer： Reese Bowes ,  Sayan Lahiri ,  Bo Qiu ,  Jianfang Olena Zhu ,  Brian A. Wilk ,  Kevin J. Daniel ,  Ana M. Yepes ,  Guodong Zhang

公开(公告)号：USD796502S1

公开(公告)日：2017-09-05

申请号：US29505654

申请日：2015-12-26

Applicant: INTEL CORPORATION

Designer： Reese Bowes ,  Sayan Lahiri ,  Bo Qiu ,  Jianfang Olena Zhu ,  Brian A. Wilk ,  Kevin J. Daniel ,  Ana M. Yepes ,  Guodong Zhang

公开(公告)号：US20240243477A1

公开(公告)日：2024-07-18

申请号：US18442331

申请日：2024-02-15

Applicant: Intel Corporation

Inventor： Erkan Alpman ,  Arnaud Lucres Amadjikpe ,  Omer Asaf ,  Kameran Azadet ,  Rotem Banin ,  Miroslav Baryakh ,  Anat Bazov ,  Stefano Brenna ,  Bryan K. Casper ,  Anandaroop Chakrabarti ,  Gregory Chance ,  Debabani Choudhury ,  Emanuel Cohen ,  Claudio Da Silva ,  Sidharth Dalmia ,  Saeid Daneshgar Asl ,  Kaushik Dasgupta ,  Kunal Datta ,  Ofir Degani ,  Amr M. Fahim ,  Amit Freiman ,  Michael Genossar ,  Eran Gerson ,  Eyal Goldberger ,  Eshel Gordon ,  Meir Gordon ,  Josef Hagn ,  Shinwon Kang ,  Te Yu Kao ,  Noam Kogan ,  Mikko S. Komulainen ,  Igal Yehuda Kushnir ,  Saku Lahti ,  Mikko M. Lampinen ,  Naftali Landsberg ,  Wook Bong Lee ,  Run Levinger ,  Albert Molina ,  Resti Montoya Moreno ,  Tawfiq Musah ,  Nathan G. Narevsky ,  Hosein Nikopour ,  Oner Orhan ,  Georgios Palaskas ,  Stefano Pellerano ,  Ron Pongratz ,  Ashoke Ravi ,  Shmuel Ravid ,  Peter Andrew Sagazio ,  Eren Sasoglu ,  Lior Shakedd ,  Gadi Shor ,  Baljit Singh ,  Menashe Soffer ,  Ra'anan Sover ,  Shilpa Talwar ,  Nebil Tanzi ,  Moshe Teplitsky ,  Chintan S. Thakkar ,  Jayprakash Thakur ,  Avi Tsarfati ,  Marian Verhelst ,  Yossi Tsfati ,  Nir Weisman ,  Shuhei Yamada ,  Ana M. Yepes ,  Duncan Kitchin

IPC: H01Q9/04 ,  H01Q1/24 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q3/24 ,  H01Q5/47 ,  H01Q21/24 ,  H03L7/14 ,  H04B1/3827 ,  H04B7/0456 ,  H04B7/06 ,  H04B15/04

CPC classification number: H01Q9/0414 ,  H01Q1/243 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q3/24 ,  H01Q5/47 ,  H01Q21/24 ,  H03L7/145 ,  H04B1/3827 ,  H04B7/0482 ,  H04B7/0639 ,  H04B15/04

Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

公开(公告)号：US20230145401A1

公开(公告)日：2023-05-11

申请号：US18089220

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Erkan Alpman ,  Arnaud Lucres Amadjikpe ,  Omer Asaf ,  Kameran Azadet ,  Rotem Banin ,  Miroslav Baryakh ,  Anat Bazov ,  Stefano Brenna ,  Bryan K. Casper ,  Anandaroop Chakrabarti ,  Gregory Chance ,  Debabani Choudhury ,  Emanuel Cohen ,  Claudio Da Silva ,  Sidharth Dalmia ,  Saeid Daneshgar Asl ,  Kaushik Dasgupta ,  Kunal Datta ,  Brandon Davis ,  Ofir Degani ,  Amr M. Fahim ,  Amit Freiman ,  Michael Genossar ,  Eran Gerson ,  Eyal Goldberger ,  Eshel Gordon ,  Meir Gordon ,  Josef Hagn ,  Shinwon Kang ,  Te Yu Kao ,  Noam Kogan ,  Mikko S. Komulainen ,  Igal Yehuda Kushnir ,  Saku Lahti ,  Mikko M. Lampinen ,  Naftali Landsberg ,  Wook Bong Lee ,  Run Levinger ,  Albert Molina ,  Resti Montoya Moreno ,  Tawfiq Musah ,  Nathan G. Narevsky ,  Hosein Nikopour ,  Oner Orhan ,  Georgios Palaskas ,  Stefano Pellerano ,  Ron Pongratz ,  Ashoke Ravi ,  Shmuel Ravid ,  Peter Andrew Sagazio ,  Eren Sasoglu ,  Lior Shakedd ,  Gadi Shor ,  Baljit Singh ,  Menashe Soffer ,  Ra'anan Sover ,  Shilpa Talwar ,  Nebil Tanzi ,  Moshe Teplitsky ,  Chintan S. Thakkar ,  Jayprakash Thakur ,  Avi Tsarfati ,  Yossi Tsfati ,  Marian Verhelst ,  Nir Weisman ,  Shuhei Yamada ,  Ana M. Yepes ,  Duncan Kitchin

IPC: H01Q9/04 ,  H01Q5/47 ,  H01Q1/24 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q3/24 ,  H01Q21/24 ,  H03L7/14 ,  H04B1/3827 ,  H04B7/0456 ,  H04B7/06 ,  H04B15/04

CPC classification number: H01Q9/0414 ,  H01Q5/47 ,  H01Q1/243 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q3/24 ,  H01Q21/24 ,  H03L7/145 ,  H04B1/3827 ,  H04B7/0482 ,  H04B7/0639 ,  H04B15/04

Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

公开(公告)号：US11233018B2

公开(公告)日：2022-01-25

申请号：US16788515

申请日：2020-02-12

Applicant: INTEL CORPORATION

Inventor： Sidharth Dalmia ,  Ana M. Yepes ,  Pouya Talebbeydokhti ,  Miroslav Baryakh ,  Omer Asaf

IPC: H01L23/34 ,  H01L23/66 ,  H01Q1/22 ,  H01L23/552 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01Q21/06 ,  H01L25/065

Abstract: Wireless modules having a semiconductor package attached to an antenna package is disclosed. The semiconductor package may house one or more electronic components as a single die package and/or a system in a package (SiP) implementation. The antenna package may be communicatively coupled to the semiconductor package using by one or more coupling pads. The antenna package may further have one or more radiating elements for transmitting and or receiving wireless signals. The antenna package and the semiconductor package may have dissimilar number of interconnect layers and/or dissimilar materials of construct.

公开(公告)号：US10686482B2

公开(公告)日：2020-06-16

申请号：US15386753

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Yaniv Michaeli ,  Menashe Soffer ,  Omer Asaf ,  Ana M. Yepes ,  Manish A. Hiranandani ,  Anand S. Konanur

IPC: H04B1/3888 ,  H04M1/02 ,  H01Q21/06 ,  H01Q13/10 ,  H01Q1/24 ,  H01Q1/42 ,  H04W88/02 ,  H04W88/08

Abstract: A metal chassis for a mobile device is configured to transmit a signal of a wavelength. A first side of the chassis faces the inside of the mobile device and includes a first aperture that has a dimension that comprises a first subwavelength width of a slot in the chassis. A second side of the chassis faces free space and includes a second aperture that has a dimension that comprises a second subwavelength width of the slot in the chassis. A channel connects the first aperture and the second aperture. The slot has a length dimension and the channel may be centered along the length dimension. The channel is configured to support a transverse electromagnetic mode for propagation of the signal from the first aperture through the channel to the second aperture. As a part of a mobile device the chassis acts as a secondary radiator for the mobile device.

公开(公告)号：US20160285428A1

公开(公告)日：2016-09-29

申请号：US14672138

申请日：2015-03-28

Applicant: Intel Corporation

Inventor： Jianfang Olena Zhu ,  Chung-Hao Joseph Chen ,  Ana M. Yepes

IPC: H03H7/38 ,  H05K1/02 ,  H03H7/01

CPC classification number: H03H7/383 ,  H03H7/0123 ,  H03H7/427 ,  H05K1/0216 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/165 ,  H05K2201/09263 ,  H05K2201/09627 ,  H05K2201/0979

Abstract: A parallel via design is disclosed to improve the impedance match for embedded common mode choke filter designs. Particularly suited to such designs on four-layer printed circuit boards, the parallel via design effectively suppresses the reflection of the differential pair. By connecting the vias in parallel, the inductance of the entire via structure is reduced while its capacitance is simultaneously increased. By properly choosing the number of parallel vias and the spacing between them, the impedance of the parallel vias can be well controlled within the frequency range of interest. Consequently, the impedance match can be improved and the return loss of a four-layer printed circuit board common mode choke filter design is reduced.

Abstract translation: 公开了并联通孔设计，以改善嵌入式共模扼流圈滤波器设计的阻抗匹配。 特别适用于四层印刷电路板上的这种设计，并行通孔设计有效地抑制了差分对的反射。 通过并联连接通孔，整个通孔结构的电感减小，同时电容同时增加。 通过适当选择并联通孔的数量和它们之间的间距，可以在感兴趣的频率范围内良好地控制并联通孔的阻抗。 因此，可以提高阻抗匹配，并且降低四层印刷电路板共模扼流滤波器设计的回波损耗。