公开(公告)号：US10886286B2

公开(公告)日：2021-01-05

申请号：US16146938

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Ashish Verma Penumatcha ,  Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L27/11514 ,  H01L27/11509 ,  G11C11/22 ,  H01L25/18 ,  H01L23/532 ,  H01L23/528

Abstract: An embodiment includes a substrate having a surface; a first layer that includes a metal and is on the substrate; a second layer that includes the metal and is on the first layer; a first switching device between the first and second layers; a second switching device between the first and second layers; a capacitor between the first and second layers, the capacitor including ferroelectric materials; a memory cell that includes the first switching device and the capacitor; an interconnect line that couples the first and second switching devices to each other; wherein: (a) the surface is substantially disposed in a first plane, and (b) a second plane is parallel to the first plane, the second plane intersecting the first and second switching devices. Other embodiments are addressed herein.

公开(公告)号：US20250113599A1

公开(公告)日：2025-04-03

申请号：US18477414

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Kirby Maxey ,  Pratyush P. Buragohain ,  Chelsey Dorow ,  Mahmut Sami Kavrik ,  Wouter Mortelmans ,  Marko Radosavljevic ,  Uygar E. Avci ,  Matthew V. Metz

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/26 ,  H01L29/66 ,  H01L29/775

Abstract: Methods for doping 2D transistor devices and resulting architectures. The use and placement of oxide dopants, such as, but not limited to, GeOx, enable control over threshold voltage performance and contact resistance of 2D transistor devices. Architectures include distinct stoichiometry compositions.

公开(公告)号：US12176388B2

公开(公告)日：2024-12-24

申请号：US16914137

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Chelsey Dorow ,  Kirby Maxey ,  Carl Naylor ,  Shriram Shivaraman ,  Sudarat Lee ,  Tanay Gosavi ,  Chia-Ching Lin ,  Uygar Avci ,  Ashish Verma Penumatcha

IPC: H01L29/04 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/267

Abstract: A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source material coupled to a first end of the first and second channel layers, a drain material coupled to a second end of the first and second channel layers, a gate electrode between the source material and the drain material, and between the first channel layer and the second channel layer and a gate dielectric between the gate electrode and each of the first channel layer and the second channel layer.

公开(公告)号：US12125893B2

公开(公告)日：2024-10-22

申请号：US18130334

申请日：2023-04-03

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-Ching Lin ,  Raseong Kim ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Ian Young

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H03H9/17

CPC classification number: H01L29/516 ,  H01L27/0886 ,  H01L29/42356 ,  H01L29/78391 ,  H01L29/7851 ,  H03H9/17

Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.

公开(公告)号：US20240222428A1

公开(公告)日：2024-07-04

申请号：US18091206

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Chelsey Dorow ,  Carl H. Naylor ,  Kirby Maxey ,  Kevin O'Brien ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Uygar Avci ,  Matthew Metz ,  Sudarat Lee ,  Ande Kitamura ,  Scott B. Clendenning ,  Mahmut Sami Kavrik

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/04 ,  H01L29/08 ,  H01L29/22 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/22 ,  H01L29/778 ,  H01L29/78696

Abstract: A transistor has multiple channel regions coupling source and drain structures, and a seed material is between one of the source or drain structures and a channel material, which includes a metal and a chalcogen. Each channel region may include a nanoribbon. A nanoribbon may have a monocrystalline structure and a thickness of a monolayer, less than 1 nm. A nanoribbon may be free of internal grain boundaries. A nanoribbon may have an internal grain boundary adjacent an end opposite the seed material. The seed material may directly contact the first of the source or drain structures, and the channel material may directly contact the second of the source or drain structures.

公开(公告)号：US20230420364A1

公开(公告)日：2023-12-28

申请号：US17849207

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Tristan A. Tronic ,  Ande Kitamura ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Chelsey Dorow ,  Kirby Maxey ,  Scott B. Clendenning ,  Sudarat Lee ,  Uygar E. Avci

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/423 ,  H01L29/18 ,  H01L27/092 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L29/42392 ,  H01L29/18 ,  H01L27/0924 ,  H01L29/78696 ,  H01L29/66742

Abstract: A microelectronic device, a semiconductor package including the device, an IC device assembly including the package, and a method of making the device. The device includes a substrate; a first structure on the substrate, the first structure corresponding to a front end of line (FEOL) stack of the device and including a plurality of first transistors therein; and a second structure on the substrate, the second structure corresponding to a back end of line (BEOL) stack of the device, and including a plurality of second transistors therein, the plurality of second transistors including a transition metal dichalcogenide (TMD) material. The second transistors are part of a voltage regulation architecture to regulate voltage supply to the die.

公开(公告)号：US20230200079A1

公开(公告)日：2023-06-22

申请号：US17555207

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Tanay A. Gosavi ,  Uygar E. Avci ,  Sou-Chi Chang ,  Hai Li ,  Dmitri Evgenievich Nikonov ,  Kaan Oguz ,  Ashish Verma Penumatcha ,  John J. Plombon ,  Ian Alexander Young

IPC: H01L27/11514 ,  H01L49/02 ,  H01L29/51

CPC classification number: H01L27/11514 ,  H01L28/65 ,  H01L29/516

Abstract: A first type of ferroelectric capacitor comprises electrodes and an insulating layer comprising ferroelectric oxides. In some embodiments, the electrodes and the insulating layer comprise perovskite ferroelectric oxides. A second type of ferroelectric capacitor comprises a ferroelectric insulating layer comprising certain monochalcogenides. Both types of ferroelectric capacitors can have a coercive voltage that is less than one volt. Such capacitors are attractive for use in low-voltage non-volatile embedded memories for next-generation semiconductor manufacturing technologies.

公开(公告)号：US20230099814A1

公开(公告)日：2023-03-30

申请号：US17485160

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kirby Maxey ,  Ashish Verma Penumatcha ,  Carl Naylor ,  Chelsey Dorow ,  Kevin O'Brien ,  Shriram Shivaraman ,  Tanay Gosavi ,  Uygar Avci

IPC: H01L29/76 ,  H01L29/24 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/443 ,  H01L29/66

Abstract: Transistors, devices, systems, and methods are discussed related to transistors including 2D material channels and heterogeneous 2D materials on the 2D material channels and coupled to source and drain metals, and their fabrication. The 2D material channels of the transistor allow for gate length scaling, improved switching performance, and other advantages and the heterogeneous 2D materials improve contact resistance of the transistor devices.

公开(公告)号：US11616130B2

公开(公告)日：2023-03-28

申请号：US16363632

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Uygar Avci ,  Devin Merrill ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Owen Loh

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

Abstract: Techniques and mechanisms to provide electrical insulation between a gate and a channel region of a non-planar circuit device. In an embodiment, the gate structure, and insulation spacers at opposite respective sides of the gate structure, each extend over a semiconductor fin structure. In a region between the insulation spacers, a first dielectric layer extends conformally over the fin, and a second dielectric layer adjoins and extends conformally over the first dielectric layer. A third dielectric layer, adjoining the second dielectric layer and the insulation spacers, extends under the gate structure. Of the first, second and third dielectric layers, the third dielectric layer is conformal to respective sidewalls of the insulation spacers. In another embodiment, the second dielectric layer is of dielectric constant which is greater than that of the first dielectric layer, and equal to or less than that of the third dielectric layer.

公开(公告)号：US20230058938A1

公开(公告)日：2023-02-23

申请号：US17409483

申请日：2021-08-23

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Dmitri Evgenievich Nikonov ,  Hai Li ,  Chia-Ching Lin ,  Raseong Kim ,  Tanay A. Gosavi ,  Ashish Verma Penumatcha ,  Uygar E. Avci ,  Marko Radosavljevic ,  Ian Alexander Young

IPC: G11C11/22 ,  H01L27/1159

Abstract: A pbit device, in one embodiment, includes a first field-effect transistor (FET) that includes a source region, a drain region, a source electrode on the source region, a drain electrode on the drain region, a channel region between the source and drain regions, a dielectric layer on a surface over the channel region, an electrode layer above the dielectric layer, and a ferroelectric (FE) material layer between the dielectric layer and the electrode layer. The pbit device also includes a second FET comprising a source electrode, a drain electrode, and a gate electrode. The drain electrode of the second FET is connected to the drain electrode of the first FET.