公开(公告)号：US20190227750A1

公开(公告)日：2019-07-25

申请号：US16370007

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Srikanth Srinivasan ,  Richard Coulson ,  Rajesh Sundaram ,  Bruce Querbach ,  Jawad B. Khan ,  Shigeki Tomishima ,  Sriram Vangal ,  Wei Wu ,  Chetan Chauhan

IPC: G06F3/06

Abstract: Technologies for performing tensor operations in memory include a memory comprising media access circuitry coupled to a memory media having a cross point architecture. The media access circuitry is to access matrix data from the memory media, perform a tensor operation on the matrix data, and write, to the memory media, resultant data indicative of a result of the tensor operation.

公开(公告)号：US10216657B2

公开(公告)日：2019-02-26

申请号：US15283186

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Bruce Querbach ,  Pete D. Vogt

IPC: G06F1/00 ,  G06F13/16 ,  G06F1/18 ,  G11C5/06

Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on thePCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module, wherein the second row of elements is positioned between the first row of elements and the third rows of elements. Other embodiments are described and claimed.

公开(公告)号：US09818457B1

公开(公告)日：2017-11-14

申请号：US15283167

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Bruce Querbach ,  Pete D. Vogt

IPC: G11C8/00 ,  G11C5/06 ,  H01R12/71 ,  G06F1/18 ,  H05K1/18

CPC classification number: G11C5/06 ,  G06F1/18 ,  G11C5/04 ,  G11C5/063 ,  G11C5/066 ,  H01R12/716 ,  H05K1/0295 ,  H05K1/141 ,  H05K1/181 ,  H05K2201/09409 ,  H05K2201/10159

Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board that includes a first row of elements including a first CPU positioned between first and second groups of dual in-line memory modules (DIMMs). The printed circuit board also includes a second row of elements including a second CPU positioned between third and fourth groups of DIMMs. The apparatus also includes a third row of elements including a fifth group of DIMMs, wherein the second row of elements is positioned between the first row of elements and the third row of elements. Other embodiments are described and claimed.

公开(公告)号：US20160378151A1

公开(公告)日：2016-12-29

申请号：US14752826

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Mark A. Schmisseur ,  Raj K. Ramanujan ,  Mohamed Arafa ,  Christopher F. Connor ,  Sudeep Puligundla ,  Mohan J. Kumar

IPC: G06F1/26 ,  G06F3/06

CPC classification number: G06F3/0685 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0652 ,  G06F3/0679 ,  G06F3/0688

Abstract: Methods and apparatus related to Rack Scale Architecture (RSA) and/or Shared Memory Controller (SMC) techniques of fast zeroing are described. In one embodiment, a storage device stores meta data corresponding to a portion of a non-volatile memory. Logic, coupled to the non-volatile memory, causes an update to the stored meta data in response to a request for initialization of the portion of the non-volatile memory. The logic causes initialization of the portion of the non-volatile memory prior to a reboot or power cycle of the non-volatile memory. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与快速归零的机架规模架构（RSA）和/或共享存储器控制器（SMC）技术相关的方法和装置。 在一个实施例中，存储设备存储对应于非易失性存储器的一部分的元数据。 耦合到非易失性存储器的逻辑响应于对非易失性存储器的该部分的初始化的请求而对存储的元数据进行更新。 在非易失性存储器的重新启动或重新启动之前，该逻辑导致非易失性存储器的该部分的初始化。 还公开并要求保护其他实施例。

公开(公告)号：US10691466B2

公开(公告)日：2020-06-23

申请号：US15943605

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Christopher Connor ,  Bruce Querbach

IPC: G06F9/4401

Abstract: Examples include techniques for booting a computing system. A processor semiconductor chip includes one or more processing cores and an embedded non-volatile random-access memory (NVRAM), the NVRAM storing instructions that when executed by the one or more processing cores manages a boot process for a computing system.

公开(公告)号：US20180190331A1

公开(公告)日：2018-07-05

申请号：US15393951

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Kuan Zhou ,  Bruce Querbach ,  Li Pan

IPC: G11C7/10

CPC classification number: G11C7/10

Abstract: An embodiment of a receiver apparatus may include high pass components to pass high frequency components of an input signal, low pass components to pass low frequency components of the input signal, and an amplifier communicatively coupled to the high pass components and the low pass components to amplify respective signals passed by the high pass components and the low pass components, wherein the low pass components include a level shifter to shift a common mode voltage level of the input signal to a switch threshold voltage for the amplifier in accordance with at least two different types of memory devices. Other embodiments are disclosed and claimed.

公开(公告)号：US09691492B1

公开(公告)日：2017-06-27

申请号：US15280669

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Bruce Querbach ,  Zion S. Kwok ,  Christopher F. Connor ,  Philip Hillier ,  Jeffrey W. Ryden

IPC: G11C5/14 ,  G11C16/28 ,  G11C16/10 ,  G11C16/30

CPC classification number: G11C16/28 ,  G11C16/10 ,  G11C16/20 ,  G11C16/30

Abstract: A predetermined pattern of bits is written to a non-volatile memory device prior to powering down the non-volatile memory device. A plurality of voltages are applied to the non-volatile memory device to determine which voltage of the plurality of voltages allows the predetermined pattern of bits to be read with a least amount of error. The determined voltage is set to be a demarcation voltage for reading from the non-volatile memory device.

公开(公告)号：US20170160338A1

公开(公告)日：2017-06-08

申请号：US14961824

申请日：2015-12-07

Applicant: Intel Corporation

Inventor： Christopher F. Connor ,  Bruce Querbach ,  Gordon McFadden ,  Hanmant P. Belgal ,  Rahul Khanna

IPC: G01R31/28 ,  G11C29/00 ,  G11C7/00

CPC classification number: G01R31/2894 ,  G11C5/04 ,  G11C7/00 ,  G11C16/3495 ,  G11C29/025 ,  G11C29/16 ,  G11C29/40 ,  G11C29/50016 ,  G11C2029/5004

Abstract: In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that include a reliability physics module stored in non-volatile memory and compute logic to calculate at least one of an estimated amount of lifetime consumed or an estimated amount of lifetime remaining after a period of operation of an integrated circuit. In embodiments, the calculation may be based at least in part on the reliability physics model and data of at least one physical condition of the integrated circuit sensed during or at the end of the period of operation. Other embodiments may be described and/or claimed.

公开(公告)号：US09659626B1

公开(公告)日：2017-05-23

申请号：US14998091

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Kuljit S. Bains ,  John B. Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4096

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096

Abstract: Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.

公开(公告)号：US11182158B2

公开(公告)日：2021-11-23

申请号：US16419483

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Shigeki Tomishima ,  Srikanth Srinivasan ,  Chetan Chauhan ,  Rajesh Sundaram

IPC: G06F12/00 ,  G06F9/30 ,  G06F9/50

Abstract: Technologies for providing adaptive memory media management include media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform at least one memory access operation to be managed by the media access circuitry. The media access circuitry is further to manage the requested at least one memory access operation, including disabling a memory controller in communication with the media access circuitry from managing the memory media while the at least one requested memory access operation is performed.