公开(公告)号：US12237223B2

公开(公告)日：2025-02-25

申请号：US17033483

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Paul A. Nyhus ,  Charles H. Wallace ,  Manish Chandhok ,  Mohit K Haran ,  Gurpreet Singh ,  Eungnak Han ,  Florian Gstrein ,  Richard E. Schenker ,  David Shykind ,  Jinnie Aloysius ,  Sean Pursel

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L27/088

Abstract: Contact over active gate (COAG) structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A remnant of a di-block-co-polymer is over a portion of the plurality of gate structures or the plurality of conductive trench contact structures. An interlayer dielectric material is over the di-block-co-polymer, over the plurality of gate structures, and over the plurality of conductive trench contact structures. An opening in the interlayer dielectric material. A conductive structure is in the opening, the conductive structure in direct contact with a corresponding one of the trench contact structures or with a corresponding one of the gate contact structures.

公开(公告)号：US20240360264A1

公开(公告)日：2024-10-31

申请号：US18766426

申请日：2024-07-08

Applicant: Intel Corporation

Inventor： Eungnak Han ,  Gurpreet Singh ,  Tayseer Mahdi ,  Florian Gstrein ,  Lauren Doyle ,  Marie Krysak ,  James Blackwell ,  Robert Bristol

IPC: C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/522 ,  H01L23/528

CPC classification number: C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/5226 ,  H01L23/528

Abstract: A chemical composition includes a polymer chain having a surface anchoring group at a terminus of the polymer chain. The surface anchoring group is metal or dielectric selective and the polymer chain further includes at least one of a photo-acid generator, quencher, or a catalyst. In some embodiments, the surface anchoring group is metal selective or dielectric selective. In some embodiments, the polymer chain includes side polymer chains where the side polymer chains include polymers of photo-acid generators, quencher, or catalyst.

公开(公告)号：US20240204083A1

公开(公告)日：2024-06-20

申请号：US18066307

申请日：2022-12-15

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Manish Chandhok ,  Florian Gstrein ,  Charles Henry Wallace ,  Eungnak Han ,  Leonard P. Guler

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L29/6656 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0655 ,  H01L29/66545 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2924/15311

Abstract: DSA-based spacers and liners can provide shorting margins for vias connected to conductive structures. Self-assembly of a diblock copolymer may be performed over a layer including conductive structures and insulative structures separating the conductive structures from each other. Spacers may be formed based on the self-assembly of the diblock copolymer. Each spacer includes an electrical insulator and is over an insulative structure. Each liner may wrap around one or more side surfaces of a spacer. Each pair of spacer and liner constitutes an insulative spacing structure that provides a shorting margin to avoid short between a via and a conductive structure not connected to the via. The insulative spacing structures may include a different electrical insulator from the insulative structures. The conductive structures may be arranged in parallel along a direction and have the same or similar heights in the direction and function as different contacts of a device.

公开(公告)号：US12002678B2

公开(公告)日：2024-06-04

申请号：US17033228

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Charles Henry Wallace ,  Mohit K. Haran ,  Paul A. Nyhus ,  Gurpreet Singh ,  Eungnak Han ,  David Nathan Shykind ,  Sean Michael Pursel

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/28123 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

公开(公告)号：US20210200085A1

公开(公告)日：2021-07-01

申请号：US16728976

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Lauren Doyle ,  Marie Krysak ,  Patrick Theofanis ,  James Blackwell ,  Eungnak Han

IPC: G03F7/039 ,  C08F30/08 ,  C08F20/24 ,  C08G83/00 ,  G03F7/20

Abstract: Chain scission resist compositions suitable for EUV lithography applications may include monomer functional groups that improve the kinetics and/or thermodynamics of the scission mechanism. Chain scission resists may include monomer functional groups that reduce the risk that leaving groups generated through the scission mechanism may chemically corrode processing equipment.

公开(公告)号：US10256141B2

公开(公告)日：2019-04-09

申请号：US15744018

申请日：2015-09-23

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Todd R. Younkin ,  Eungnak Han ,  Jasmeet S. Chawla ,  Marie Krysak ,  Hui Jae Yoo ,  Tristan A. Tronic

IPC: H01L21/331 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.

公开(公告)号：US12087594B2

公开(公告)日：2024-09-10

申请号：US17124730

申请日：2020-12-17

Applicant: INTEL CORPORATION

Inventor： Gurpreet Singh ,  Eungnak Han ,  Manish Chandhok ,  Richard E Schenker ,  Florian Gstrein ,  Paul A. Nyhus ,  Charles Henry Wallace

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76831

Abstract: Disclosed herein are colored gratings in microelectronic structures. For example, a microelectronic structure may include first conductive structures alternating with second conductive structures, wherein individual ones of the first conductive structures include a bottom portion and a top portion, individual cap structures are on individual ones of the second conductive structures, the bottom portions of the first conductive structures are laterally spaced apart from and aligned with the second conductive structures, and the top portions of the first conductive structures are laterally spaced apart from and aligned with the cap structures. In some embodiments, a microelectronic structure may include one or more unordered lamellar regions laterally spaced apart from and aligned with the first conductive structures.

公开(公告)号：US20240249946A1

公开(公告)日：2024-07-25

申请号：US18625348

申请日：2024-04-03

Applicant: Intel Corporation

Inventor： Charles Henry Wallace ,  Mohit K. Haran ,  Paul A. Nyhus ,  Gurpreet Singh ,  Eungnak Han ,  David Nathan Shykind ,  Sean Michael Pursel

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/28123 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

公开(公告)号：US20240222119A1

公开(公告)日：2024-07-04

申请号：US18147107

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Eungnak Han ,  James Blackwell ,  Gurpreet Singh ,  Florian Gstrein

IPC: H01L21/027 ,  H01L21/02

CPC classification number: H01L21/0274 ,  H01L21/02118 ,  H01L21/02345 ,  C08F293/00

Abstract: In-situ formation of a block copolymer through deprotection can provide patterns with flexible pitches. A layer of a protected polymer including a protecting group is formed. One or more portions of the layer may be exposed to light. The exposed portion(s) may be baked after the light exposure. The protecting group is removed after the light exposure or bake so that the protected polymer becomes a deprotected polymer in the exposure portion(s). The deprotected polymer is bonded with the protected polymer in the unexposed portion(s) of the layer but has a different solubility from the protected polymer so that phases of the block copolymer are separated. The phase separation can provide a periodic pattern with various pitches. The solution and roughness of the pattern can be enhanced by using CARs formed with a protected, cross-linked polymer that includes a protective group and a function group with a ratio of 50:50.

公开(公告)号：US11953826B2

公开(公告)日：2024-04-09

申请号：US17464393

申请日：2021-09-01

Applicant: Intel Corporation

Inventor： James M. Blackwell ,  Robert L. Bristol ,  Marie Krysak ,  Florian Gstrein ,  Eungnak Han ,  Kevin L. Lin ,  Rami Hourani ,  Shane M. Harlson

IPC: G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  H01L21/768

CPC classification number: G03F7/0035 ,  G03F7/0002 ,  G03F7/40 ,  H01L21/027 ,  H01L21/0274 ,  H01L21/768 ,  H01L21/76802

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.