公开(公告)号：US20170330966A1

公开(公告)日：2017-11-16

申请号：US15525183

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  STEPHEN M. CEA ,  TAHIR GHANI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7831 ,  H01L29/0607 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: An embodiment includes an apparatus comprising: a fin structure on a substrate, the fin structure including fin top and bottom portions, a channel including a majority carrier, and an epitaxial (EPI) layer; an insulation layer including insulation layer top and bottom portions adjacent the fin top and bottom portions; wherein (a) the EPI layer comprises one or more of group IV and III-V materials, (b) the fin bottom portion includes a fin bottom portion concentration of dopants of opposite polarity to the majority carrier, (c) the fin top portion includes a fin top portion concentration of the dopants less than the fin bottom portion concentration, (d) the insulation layer bottom portion includes an insulation layer bottom portion concentration of the dopants, and (e) the insulation layer top portion includes an insulation top layer portion concentration greater than the insulation bottom portion concentration. Other embodiments are described herein.

公开(公告)号：US20170133376A1

公开(公告)日：2017-05-11

申请号：US15115825

申请日：2014-03-24

Applicant: Intel Corporation

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  DANIEL B. AUBERTINE ,  SUBHASH M. JOSHI

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/3065

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: Techniques are disclosed for sculpting and cladding the channel region of fins on a semiconductor substrate during a replacement gate process (e.g., for transistor channel applications). The sculpting and cladding can be performed when the channel region of the fins are re-exposed after the dummy gate used in the replacement gate process is removed. The sculpting includes performing a trim etch on the re-exposed channel region of the fins to narrow a width of the fins (e.g., by 2-6 nm). A cladding layer, which may include germanium (Ge) or silicon germanium (SiGe), can then be deposited on the trimmed fins, leaving the source/drain regions of the fins unaffected. The sculpting and cladding may be performed in-situ or without air break to increase the quality of the trimmed fins (e.g., as compared to an ex-situ process).

公开(公告)号：US20160027781A1

公开(公告)日：2016-01-28

申请号：US14875167

申请日：2015-10-05

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/267

CPC classification number: H01L29/78618 ,  H01L21/76805 ,  H01L21/76886 ,  H01L21/76895 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures.

公开(公告)号：US20210005712A1

公开(公告)日：2021-01-07

申请号：US17025077

申请日：2020-09-18

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY

IPC: H01L29/06 ,  H01L21/285 ,  H01L29/165 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/167 ,  H01L21/02 ,  H01L29/08 ,  H01L29/36 ,  H01L27/092 ,  H01L23/535 ,  H01L29/417 ,  H01L21/3215 ,  H01L21/768 ,  H01L29/778

Abstract: Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.

公开(公告)号：US20200006229A1

公开(公告)日：2020-01-02

申请号：US16337794

申请日：2016-10-28

Applicant: INTEL CORPORATION

Inventor： SEUNG HOON SUNG ,  GLENN A. GLASS ,  VAN H. LE ,  ASHISH AGRAWAL ,  BENJAMIN CHU-KUNG ,  ANAND S. MURTHY ,  JACK T. KAVALIEROS

IPC: H01L23/535 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L27/092

Abstract: Techniques are disclosed for forming transistor devices having reduced interfacial resistance in a local interconnect. The local interconnect can be a material having similar composition to that of the source/drain material. That composition can be a metal alloy of a group IV element such as nickel germanide. The local interconnect of the semiconductor integrated circuit can function in the absence of barrier and liner layers. The devices can be used on MOS transistors including PMOS transistors.

公开(公告)号：US20190207015A1

公开(公告)日：2019-07-04

申请号：US16322815

申请日：2016-09-27

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  CORY E. WEBER ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  JIONG ZHANG ,  RITESH JHAVERI ,  SZUYA S. LIAO

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/32 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Techniques are disclosed for forming increasing channel region tensile strain in n-MOS devices. In some cases, increased channel region tensile strain can be achieved via S/D material engineering that deliberately introduces dislocations in one or both of the S/D regions to produce tensile strain in the adjacent channel region. In some such cases, the S/D material engineering to create desired dislocations may include using a lattice mismatched epitaxial S/D film adjacent to the channel region. Numerous material schemes for achieving multiple dislocations in one or both S/D regions will be apparent in light of this disclosure. In some cases, a cap layer can be formed on an S/D region to reduce contact resistance, such that the cap layer is an intervening layer between the S/D region and S/D contact. The cap layer includes different material than the underlying S/D region and/or a higher dopant concentration to reduce contact resistance.

公开(公告)号：US20190109234A1

公开(公告)日：2019-04-11

申请号：US16199445

申请日：2018-11-26

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI ,  YING PANG ,  NABIL G. MISTKAWI

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L27/092 ,  H01L29/167 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/417 ,  H01L29/66 ,  H01L29/165 ,  H01L29/45 ,  H01L21/306 ,  H01L21/762 ,  H01L21/02 ,  H01L29/161 ,  H01L29/786

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3.

公开(公告)号：US20180248004A1

公开(公告)日：2018-08-30

申请号：US15753739

申请日：2015-09-18

Applicant: INTEL CORPORATION

Inventor： PRASHANT MAJHI ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI ,  ARAVIND S. KILLAMPALLI ,  MARK R. BRAZIER ,  JAYA P. GUPTA

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/775 ,  H01L29/78 ,  H01L27/092 ,  H01L21/30

Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides. Such interfaces are common locations of trap sites that may include impurities, incomplete bonds dangling bonds, and broken bonds, for example, and thus such interfaces can benefit from deuterium-based passivation to improve the performance and reliability of the transistor.

公开(公告)号：US20180158944A1

公开(公告)日：2018-06-07

申请号：US15576381

申请日：2015-06-23

Applicant: INTEL CORPORATION

Inventor： CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  GLENN A. GLASS ,  TAHIR GHANI ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  GILBERT DEWEY ,  MATTHEW V. METZ ,  HAROLD W. KENNEL

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/12 ,  H01L29/775 ,  H01L29/66 ,  H01L29/205 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L21/02241 ,  H01L27/0886 ,  H01L29/1054 ,  H01L29/125 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/775

Abstract: Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure.

公开(公告)号：US20180158841A1

公开(公告)日：2018-06-07

申请号：US15576393

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  DANIEL B. AUBERTINE ,  TAHIR GHANI ,  JACK T. KAVALIEROS ,  BENJAMIN CHU-KUNG ,  CHANDRA S. MOHAPATRA ,  KARTHIK JAMBUNATHAN ,  GILBERT DEWEY ,  WILLY RACHMADY

IPC: H01L27/12 ,  H01L29/161 ,  H01L29/20 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L27/1211 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced. The sacrificial fins can be thought of as cores and can be implemented, for example, with material native to the substrate or a replacement material that enables low-defect exotic cladding materials combinations.