公开(公告)号：US20150249298A1

公开(公告)日：2015-09-03

申请号：US14563641

申请日：2014-12-08

Applicant: Intel Corporation

Inventor： Gaurav Chawla ,  Joshua D. Heppner ,  Zhichao Zhang ,  David J. Llapitan ,  Vijaykumar Krithivasan

IPC: H01R12/72 ,  H01R12/70 ,  H01L23/34 ,  H01R13/11

CPC classification number: H01R12/722 ,  H01L23/34 ,  H01L2924/0002 ,  H01R12/7005 ,  H01R12/71 ,  H01R12/724 ,  H01R12/79 ,  H01R13/114 ,  H01L2924/00

Abstract: Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port.

Abstract translation: 显示连接器和耦合封装和管芯的方法。 所选择的示例包括具有两个或更多台阶的插头和插座，其具有沿着梯田提供的触点。 连接器和方法的示例包括其中连接器可用于包括沿衬底耦合的裸片的封装的配置。 在所选择的示例中，散热器耦合在管芯上，并且封装包括在散热器和被配置为接收连接器的基板之间的侧入口，例如通过侧面接入端口的一个或多个插头或插座。

公开(公告)号：US08915747B2

公开(公告)日：2014-12-23

申请号：US13826998

申请日：2013-03-14

Applicant: Intel Corporation

Inventor： Gaurav Chawla ,  Rajasekaran Raja Swaminathan ,  Donald T. Tran

IPC: H01R12/00 ,  H01R12/71

CPC classification number: H01R12/71 ,  H01R12/53 ,  H01R12/57 ,  H01R25/006

Abstract: This disclosure relates generally to a connector assembly. Optionally, first conductive members form a first row. Second conductive members include a first subset forming a second row and a second subset forming a third row, the second and third rows being parallel and offset with respect to one another. Individual ones of the first and second conductive members are arranged to be coupled at a first end to a corresponding contact. At least one of the first and second subsets has a vertical displacement to form a common row of the second conductive members at a second end of the second conductive members. Individual ones of the first conductive members are arranged to be coupled proximate a second end of the first conductive members to the second end of a corresponding one of the second conductive members.

Abstract translation: 本公开总体上涉及连接器组件。 可选地，第一导电构件形成第一行。 第二导电构件包括形成第二行的第一子集和形成第三行的第二子集，第二和第三行相对于彼此平行和偏移。 第一和第二导电构件中的各个被布置成在第一端耦合到相应的触点。 第一和第二子集中的至少一个具有垂直位移，以在第二导电构件的第二端处形成第二导电构件的公共排。 第一导电构件中的各个被布置成在第一导电构件的第二端附近耦合到相应的一个第二导电构件的第二端。

公开(公告)号：US10044115B2

公开(公告)日：2018-08-07

申请号：US14757626

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Donald T. Tran ,  Gregorio Murtagian ,  Kuang Liu ,  Srikant Nekkanty ,  Feroz Mohammad ,  Karumbu Meyyappan ,  Hong Xie ,  Russell S. Aoki ,  Gaurav Chawla

IPC: H01R4/50 ,  H01R13/639 ,  H01R4/52 ,  H01R13/508 ,  H01R12/85 ,  H01R12/72

Abstract: An apparatus comprises a cable connector including: a first connector body portion including a first plurality of electrical contacts arranged to contact electrical contacts of a first surface of an edge connector substrate; a second connector body portion separate from the first connector body portion and including a second plurality of electrical contacts arranged to oppose the first plurality of electrical contacts of the first connector body portion and to contact electrical contacts of a second surface of the edge connector substrate, wherein the first and second plurality of electrical contacts are electrically coupled to one or more cables; and a joining mechanism configured to join the first connector body portion and the second connector body portion together and to apply a bias force to the edge connector substrate when the edge connector substrate is arranged between the first connector body portion and the second connector body portion.

公开(公告)号：US20180019558A1

公开(公告)日：2018-01-18

申请号：US15716356

申请日：2017-09-26

Applicant: INTEL CORPORATION

Inventor： Dhanya Athreya ,  Gaurav Chawla ,  Kemal Aygun ,  Glen P. Gordon ,  Sarah M. Canny ,  Jeffory L. Smalley ,  Srikant Nekkanty ,  Michael Garcia ,  Joshua D. Heppner

IPC: H01R33/76 ,  H01L23/32 ,  H01L23/498

CPC classification number: H01R33/7685 ,  H01L23/32 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.

公开(公告)号：US09848510B2

公开(公告)日：2017-12-19

申请号：US14578037

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： Vijaykumar Krithivasan ,  Jeffory L. Smalley ,  David J. Llapitan ,  Gaurav Chawla ,  Mani Prakash ,  Susan F. Smith

IPC: H01L23/32 ,  H05K7/20 ,  H01L23/36 ,  H01L23/40

CPC classification number: H05K7/2039 ,  H01L23/32 ,  H01L23/36 ,  H01L23/40 ,  H01L2924/0002 ,  H05K2201/10378 ,  H05K2201/1056 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards a socket loading element and associated techniques and configurations. In one embodiment, an apparatus may include a loading element configured to transfer a compressive load from a heat spreader to a socket assembly, wherein the loading element is configured to form a perimeter around a die when the loading element is coupled with an interposer disposed between the die and the socket assembly and wherein the loading element includes an opening configured to accommodate the die. Other embodiments may be described and/or claimed.

公开(公告)号：US09603276B2

公开(公告)日：2017-03-21

申请号：US14583372

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： David J. Llapitan ,  Jeffory L. Smalley ,  Gaurav Chawla ,  Joshua D Heppner ,  Vijaykumar Krithivasan ,  Jonathan W. Thibado ,  Kuang Liu ,  Gregorio Murtagian

IPC: H01R12/00 ,  H05K7/10

CPC classification number: H05K7/1084

Abstract: Some forms relate to an electronic assembly that includes a plurality of electronic package. The electronic assembly includes a frame and a first electronic package mounted on the frame. The first electronic package includes a first pin grid array. The electronic assembly further includes a second electronic package mounted on the frame. The second electronic package includes a second pin grid array. The electronic assembly further includes an actuation mechanism on the frame. The actuation mechanism is configured to move the first electronic package and the second electronic package relative to the frame during operation of the actuation mechanism.

公开(公告)号：US20160254629A1

公开(公告)日：2016-09-01

申请号：US14764931

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Dhanya Athreya ,  Gaurav Chawla ,  Kemal Aygun ,  Glen P. Gordon ,  Sarah M. Canny ,  Jeffory L. Smalley ,  Srikant Nekkanty ,  Michael Garcia ,  Joshua D. Heppner

IPC: H01R33/76 ,  H01L23/32

CPC classification number: H01R33/7685 ,  H01L23/32 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例针对套接触接触技术和配置。 在一个实施例中，装置可以包括具有第一侧和与第一侧相对设置的第二侧的插座衬底，通过插座衬底形成的开口，设置在开口中并被配置为在第一 所述电接触件具有延伸超过所述第一侧面的悬臂部分，其中所述开口中的所述插座基板的所述第一侧面和所述表面镀有金属。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09265170B2

公开(公告)日：2016-02-16

申请号：US14065281

申请日：2013-10-28

Applicant: INTEL CORPORATION

Inventor： Rajasekaran Swaminathan ,  Ram S. Viswanath ,  Sanka Ganesan ,  Gaurav Chawla ,  Joshua D. Heppner ,  Jeffory L. Smalley ,  Vijaykumar Krithivasan ,  David J. Llapitan ,  Neal E. Ulen ,  Donald T. Tran

IPC: H01R12/00 ,  H05K1/00 ,  H05K7/10 ,  H01R12/71 ,  H01R13/24

CPC classification number: H05K7/10 ,  H01R12/00 ,  H01R12/716 ,  H01R13/2442 ,  H05K1/00 ,  Y10T29/49169

Abstract: Embodiments related to integrated circuit (IC) connectors are described. In some embodiments, an IC assembly may include an IC package substrate, an intermediate member, and a male connector. The IC package substrate may have first signal contacts on a top or bottom surface, and the bottom surface may have second signal contacts for coupling with a socket on a circuit board. The intermediate member may have a first end coupled to the first signal contacts and a second end extending beyond the side surface. The male connector may be disposed at the second end of the intermediate member, and may have signal contacts coupled to the signal contacts of the intermediate member. The male connector may be mateable with a female connector when the female connector is brought into engagement in a direction parallel to the axis of the intermediate member. Other embodiments may be disclosed and/or claimed.

Abstract translation: 描述了与集成电路（IC）连接器相关的实施例。 在一些实施例中，IC组件可以包括IC封装衬底，中间构件和阳连接器。 IC封装基板可以在顶表面或底表面上具有第一信号触点，并且底表面可以具有用于与电路板上的插座耦合的第二信号触点。 中间构件可以具有联接到第一信号触头的第一端和延伸超过侧表面的第二端。 阳连接器可以设置在中间构件的第二端处，并且可以具有联接到中间构件的信号触点的信号触点。 当阴连接器沿平行于中间构件的轴线的方向接合时，阳连接器可与母连接器配合。 可以公开和/或要求保护其他实施例。

公开(公告)号：US20150162719A1

公开(公告)日：2015-06-11

申请号：US14626648

申请日：2015-02-19

Applicant: Intel Corporation

Inventor： Gaurav Chawla ,  Vijaykumar Krithivasan ,  Joshua D. Heppner

IPC: H01R43/20

CPC classification number: H01R43/20 ,  H01R24/86 ,  H05K7/1084 ,  Y10T29/4922

Abstract: An apparatus for coupling an integrated circuit to other electronics can include a housing having an exterior and an interior, the exterior having an exterior bottom surface, the interior defined by an interior bottom surface opposite the exterior bottom surface, and at least one sidewall extending away from the interior bottom surface to define an interior shape that is sized to receive the integrated circuit, with the integrated circuit disposed against the interior bottom surface and the at least one sidewall. The example can include a plurality of exterior contacts exposed along the exterior bottom surface in an exterior contact pattern that is generally circular in shape.

Abstract translation: 用于将集成电路耦合到其它电子设备的装置可以包括具有外部和内部的外壳，外部具有外部底部表面，内部由与外部底部表面相对的内部底部表面限定，并且至少一个侧壁延伸远离 从内部底部表面限定尺寸适于接收集成电路的内部形状，其中集成电路抵靠内部底部表面和至少一个侧壁设置。 该示例可以包括沿着外部底部表面暴露的多个外部接触件，外部接触图案通常为圆形形状。

公开(公告)号：US11516915B2

公开(公告)日：2022-11-29

申请号：US16559286

申请日：2019-09-03

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Tao Wu ,  Gaurav Chawla ,  Jeffrey Lee

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H05K3/34 ,  H05K1/02

Abstract: A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.