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公开(公告)号：US09766678B2
公开(公告)日：2017-09-19
申请号：US13758897
申请日：2013-02-04
Applicant: Intel Corporation
Inventor： Ramnarayanan Muthukaruppan , Harish K. Krishnamurthy , Mohit Verma , Pradipta Patra , Uday Bhaskar Kadali
CPC classification number: G06F1/32 , G06F1/324 , G06F1/3243 , G06F1/3296 , Y02D10/152 , Y02D10/172
Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.
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公开(公告)号：US20160190921A1
公开(公告)日：2016-06-30
申请号：US14582956
申请日：2014-12-24
Applicant: Intel Corporation
Inventor： Pavan Kumar , Harish K. Krishnamurthy
IPC: H02M3/158
CPC classification number: H02M3/158 , H02M3/07 , H02M2001/0045
Abstract: One embodiment provides an apparatus. The apparatus includes a selectable-mode voltage regulator (VR) to implement one or more of a plurality of VR modes. The selectable-mode VR includes a plurality of switches, an inductor (L), a flying capacitor (Cf), and an output capacitor (Cout).
Abstract translation: 一个实施例提供了一种装置。 该装置包括用于实现多个VR模式中的一个或多个的可选模式电压调节器（VR）。 可选模式VR包括多个开关，电感器（L），飞行电容器（Cf）和输出电容器（Cout）。
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公开(公告)号：US20230205244A1
公开(公告)日：2023-06-29
申请号：US17561109
申请日：2021-12-23
Applicant: Intel Corporation
Inventor： Anand Ramasundar , Cary Renzema , Fabrice Paillet , James Keith Hodgson , Po-Cheng Chen , Sergio Carlo Rodriguez , Harish K. Krishnamurthy , Jason Muhlestein
Abstract: An apparatus, system, and method for digital voltage regulator (DVR) control are provided. A DVR includes comparators configured to determine whether VLOAD drops below a gradual non-linear control (NLC) undershoot threshold voltage, rises above or drops below a reference voltage, and rises above a gradual NLC overshoot threshold voltage, respectively, power gates (PGs) configured to adjust VOUT based on a provided PG code; and VR controller circuitry comprising synchronous LC circuitry configured to increase or decrease, by a first increment, the PG code responsive to the VLOAD dropping below the reference voltage and rising above the reference voltage, and asynchronous gradual NLC circuitry configured to increase or decrease, by a second increment greater than the first increment and less than half a maximum PG code value, the PG code responsive to the VLOAD dropping below the gradual NLC undershoot threshold voltage and rising above the gradual NLC overshoot threshold voltage.
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公开(公告)号：US20220374060A1
公开(公告)日：2022-11-24
申请号：US17323837
申请日：2021-05-18
Applicant: Intel Corporation
Inventor： Harish K. Krishnamurthy , Xun Sun , Krishnan Ravichandran
Abstract: A computational current sensor, that enhances traditional Kalman filter based current observer techniques, with transient tracking enhancements and an online parasitic parameter identification that enhances overall accuracy during steady state and transient events while guaranteeing convergence. During transient operation (e.g., a voltage droop), a main filter is bypassed with estimated values calculated from a charge balance principle to enhance accuracy while tracking transient current surges of the DC-DC converter. To address the issue of dependency on a precise model parameter information and further improve accuracy, an online identification algorithm is included to track the equivalent parasitic resistance at run-time.
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15.发明申请公开(公告)号：US20190094931A1
公开(公告)日：2019-03-28
申请号：US15718991
申请日：2017-09-28
Applicant: INTEL CORPORATION
Inventor： Khondker Z. Ahmed , Vivek K. De , Nachiket V. Desai , Suhwan Kim , Harish K. Krishnamurthy , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram R. Vangal
Abstract: Various embodiments of the invention may analyze previous patterns of harvested energy to predict future patterns of available harvested energy. This prediction may then be used to choose from among multiple methods of energy reduction techniques. The energy reduction techniques may include multiple versions of reducing or modifying instruction execution. Reduced instruction execution may include reducing the precision of various calculations.
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Patent Agency Ranking
公开(公告)号：US09882383B2
公开(公告)日：2018-01-30
申请号：US14581903
申请日：2014-12-23
Applicant: INTEL CORPORATION
Inventor： Harish K. Krishnamurthy , Khondker Z. Ahmed , Krishnan Ravichandran
CPC classification number: H02J3/00 , G06F1/26 , G06F1/263 , G06F1/324 , G06F1/3243 , G06F1/3296 , H02J1/10
Abstract: Examples may include a smart power delivery network using voltage regulators to supply combined power sufficient to meet a peak load demand generated from one load from among multiple possible loads. A system of power gate devices having controllers may assist in dynamically steering current driven by the voltage regulators to the multiple possible loads.
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公开(公告)号：US09710422B2
公开(公告)日：2017-07-18
申请号：US14570898
申请日：2014-12-15
Applicant: Intel Corporation
Inventor： Sheldon Weng , George E. Matthew , Pavan Kumar , Wayne L. Proefrock , Harish K. Krishnamurthy , Krishnan Ravichandran
IPC: G06F13/42 , G06F13/364 , G06F13/40 , G06F1/32 , G06F1/26
CPC classification number: G06F13/4282 , G06F1/26 , G06F1/3203 , G06F1/3253 , G06F13/364 , G06F13/404 , G06F2213/0052 , Y02D10/151
Abstract: Methods and apparatus relating to low cost and/or low overhead serial interface for power management and other IC (Integrated Circuit) devices are described. In an embodiment, a unique address is assigned to each of a plurality of slave devices. The plurality of slave devices are coupled in a daisy chain configuration. And, any access directed at a first slave device from the plurality of slave devices is allowed based at least in part on comparison of an address of the first slave device and an address associated with the access. Other embodiments are also disclosed and claimed.
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18.发明申请公开(公告)号：US20250103075A1
公开(公告)日：2025-03-27
申请号：US18474156
申请日：2023-09-25
Applicant: Intel Corporation
Inventor： Khondker Ahmed , Nicolas Butzen , Nachiket Desai , Su Hwan Kim , Harish K. Krishnamurthy , Krishnan Ravichandran , Kaladhar Radhakrishnan , Jonathan Douglas
IPC: G05F1/56
Abstract: Embodiments herein relate to a stacked semiconductor structure which includes a first voltage regulator (VR), external to a package, for supplying current to a compute die in the package. When the required current exceeds a threshold, an additional current source is activated. The additional current source can include a second VR, also external to the package, for supplying current to an integrated voltage regulator (IVR) in the package. The IVR performs voltage down conversion and current multiplication to output a portion of the required current above the threshold, while the output of the first VR is capped at the threshold.
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19.发明授权公开(公告)号：US10958079B2
公开(公告)日：2021-03-23
申请号：US15939120
申请日：2018-03-28
Applicant: Intel Corporation
Inventor： Xiaosen Liu , Khondker Z. Ahmed , Vivek K. De , Nachiket V. Desai , Suhwan Kim , Harish K. Krishnamurthy , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav A. Vaidya , Sriram R. Vangal
Abstract: In one embodiment, an energy harvesting system includes multiple-input-multiple-output switched-capacitor (MIMOSC) circuitry comprising a plurality of switched-capacitor circuit units to receive a plurality of direct current (DC) input voltages at respective input terminals of the switched-capacitor circuit unit, combine the received DC input voltages, and provide the combined DC input voltages at an output terminal of the switched-capacitor circuit unit. The energy harvesting system also includes maximum power point tracking (MPPT) circuitry coupled to switches of the switched-capacitor circuit units of the MIMOSC circuitry. The MPPT circuitry is to provide a plurality of switching signals to the switches of the switched-capacitor circuit units. The MIMOSC circuitry is to provide a plurality of DC output voltages to respective loads based on the switching signals from the MPPT circuitry.
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公开(公告)号：US10942556B2
公开(公告)日：2021-03-09
申请号：US15682724
申请日：2017-08-22
Applicant: Intel Corporation
Inventor： Dileep J. Kurian , Ankit Gupta , Akhila M , Tanay Karnik , Vaibhav Vaidya , David Arditti Ilitzky , Christopher Schaef , Sriram Kabisthalam Muthukumar , Harish K. Krishnamurthy , Suhwan Kim
IPC: G06F1/3203 , G06F1/3212 , G06F1/26 , H02J7/34 , H02J7/00
Abstract: Systems, apparatuses and methods may provide for early pre-charge with respect to peak power events. Application performance may improve by pre-charging a supercap just prior to initiating a system wake up from a qualified system wake-source trigger. Additionally, the pre-charging of the supercap may be controlled by a time defined pre-charge period and may also be controlled by a predetermined threshold voltage.
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