公开(公告)号：US20220069810A1

公开(公告)日：2022-03-03

申请号：US17006726

申请日：2020-08-28

Applicant: Intel Corporation

Inventor： Nachiket Desai ,  Suhwan Kim ,  Harish Krishnamurthy ,  Christopher Schaef

IPC: H03K3/037 ,  H03K5/24 ,  H03K17/687

Abstract: A digital self-start controller, which is functional without fuse and/or trim information. The self-start controller protects a DC-DC converter against large inrush currents and voltage overshoots, while being capable of following a variable VID (voltage identification) reference ramp imposed by the system. The self-start controller uses a relaxation oscillator to set the switching frequency of the DC-DC converter. The oscillator can be initialized using either a clock or current reference to be close to a desired operating frequency. The output of the DC-DC converter is coupled weakly to the oscillator to set the duty cycle for closed loop operation. The controller is naturally biased such that the output supply voltage is always slightly higher than a set point, eliminating the need for any process, voltage, and/or temperature (PVT) imposed trims.

公开(公告)号：US11205962B2

公开(公告)日：2021-12-21

申请号：US16409562

申请日：2019-05-10

Applicant: Intel Corporation

Inventor： Nachiket Desai ,  Harish Krishnamurthy ,  Suhwan Kim

IPC: G06F1/26 ,  H02M1/14 ,  H02M3/158 ,  H02M3/157 ,  H02M3/15 ,  H02M1/00

Abstract: An apparatus is described which includes a delay-line with reasonably matched delay cells and some logic to ascertain both a correct number of DC-DC converters and interleaving angles or phase offsets. The apparatus measures an operating frequency in real-time in multiples of the individual delay cells of the delay-line. The smaller the period, the higher the load coupled to the DC-DC converters and, therefore the greater the number of DC-DC converters are needed to service the load. The period determines the load and can be used to determine the number of DC-DC converters needed and thereby accomplishing autonomous phase enabling/shedding.

公开(公告)号：US20210271277A1

公开(公告)日：2021-09-02

申请号：US17253096

申请日：2019-09-06

Applicant: Intel Corporation

Inventor： Khondker Ahmed ,  Harish Krishnamurthy ,  Krishnan Ravichandran

IPC: G05F1/575 ,  G06F1/26

Abstract: A Computational Digital Low Dropout (CDLDO) regulator is described that computes a required solution for regulating an output supply as opposed to traditional feedback controllers. The CDLDO regulator is Moore's Law friendly in that it can scale with technology nodes. For example, CDLDO regulator of some embodiments uses a digital approach to voltage regulation, which is orders of magnitude faster than traditional digital LDOs and enables regulation at GHz speeds, making fast dynamic DVFS a reality. The CDLDO also autonomously tunes out the effects of process-voltage-temperature (PVT) and other non-idealities making the settling time totally variation tolerant.

公开(公告)号：US20210208656A1

公开(公告)日：2021-07-08

申请号：US16735563

申请日：2020-01-06

Applicant: Intel Corporation

Inventor： Alexander Uan-Zo-Li ,  Eugene Gorbatov ,  Harish Krishnamurthy ,  Alexander Lyakhov ,  Patrick Leung ,  Stephen Gunther ,  Arik Gihon ,  Khondker Ahmed ,  Philip Lehwalder ,  Sameer Shekhar ,  Vishram Pandit ,  Nimrod Angel ,  Michael Zelikson

IPC: G06F1/32 ,  G05F1/56

Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

公开(公告)号：US20210103308A1

公开(公告)日：2021-04-08

申请号：US17100603

申请日：2020-11-20

Applicant: Intel Corporation

Inventor： Xiaosen Liu ,  Harish Krishnamurthy ,  Krishnan Ravichandran ,  Vivek De ,  Scott Chiu ,  Claudia Patricia Barrera Gonzalez ,  Jing Han ,  Rajasekhara Madhusudan Narayana Bhatla

IPC: G05F1/56 ,  G05F1/46 ,  G05F1/67

Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.

公开(公告)号：US10298117B2

公开(公告)日：2019-05-21

申请号：US15638643

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Harish Krishnamurthy ,  Khondker Ahmed ,  Vivek De ,  Nachiket Desai ,  Suhwan Kim ,  Xiaosen Liu ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav Vaidya ,  Sriram Vangal

IPC: H04W84/20 ,  H02M1/42 ,  H03M1/00 ,  H02M1/00 ,  H02M1/084 ,  H02M3/158

Abstract: Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.

公开(公告)号：US20180375433A1

公开(公告)日：2018-12-27

申请号：US15632086

申请日：2017-06-23

Applicant: INTEL CORPORATION

Inventor： Khondker Ahmed ,  Vivek De ,  Nachiket Desai ,  Suhwan Kim ,  Harish Krishnamurthy ,  Xiaosen Liu ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav Vaidya ,  Sriram Vangal

IPC: H02M3/158 ,  H02M1/08

CPC classification number: H02M3/1582 ,  G05F1/67 ,  H02M1/08 ,  H02M2001/0003 ,  H02M2001/0009 ,  H02M2001/0025

Abstract: Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.

公开(公告)号：US12166414B2

公开(公告)日：2024-12-10

申请号：US17711461

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Tamir Salus ,  Nicolas Butzen ,  Arvind Raghavan ,  Harish Krishnamurthy

IPC: H02M3/07 ,  G01R19/25

Abstract: Techniques and mechanisms for determining a mode of operation of a switched capacitor voltage regulator (SCVR). In an embodiment, a controller supports multiple modes of operation of the SCVR, wherein the modes each correspond to a different respective sequence of switch states of a converter core of the SCVR. One of the modes is to provide boost voltage regulation with the SCVR. The controller transitions seamlessly and autonomously between two modes based on respective reference switch states of the two modes. In another embodiment, a mode transition is performed based on a signal which a control sensor generates based on a rate of switch events of the voltage regulator, and predetermined reference information indicating current characteristics of the voltage regulator.

公开(公告)号：US20230318448A1

公开(公告)日：2023-10-05

申请号：US17711461

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Tamir Salus ,  Nicolas Butzen ,  Arvind Raghavan ,  Harish Krishnamurthy

IPC: H02M3/07 ,  G01R19/25

CPC classification number: H02M3/07 ,  G01R19/25

Abstract: Techniques and mechanisms for determining a mode of operation of a switched capacitor voltage regulator (SCVR). In an embodiment, a controller supports multiple modes of operation of the SCVR, wherein the modes each correspond to a different respective sequence of switch states of a converter core of the SCVR. One of the modes is to provide boost voltage regulation with the SCVR. The controller transitions seamlessly and autonomously between two modes based on respective reference switch states of the two modes. In another embodiment, a mode transition is performed based on a signal which a control sensor generates based on a rate of switch events of the voltage regulator, and predetermined reference information indicating current characteristics of the voltage regulator.

公开(公告)号：US11747371B2

公开(公告)日：2023-09-05

申请号：US17006715

申请日：2020-08-28

Applicant: Intel Corporation

Inventor： Nachiket Desai ,  Harish Krishnamurthy ,  Suhwan Kim ,  Fabrice Paillet

IPC: G01R19/00 ,  H03F1/34 ,  H03F3/45 ,  H02M3/158 ,  G01R1/30 ,  H03F1/42 ,  G05F3/26 ,  H02M1/00

CPC classification number: G01R19/0023 ,  G01R1/30 ,  G05F3/262 ,  H02M3/158 ,  H03F1/34 ,  H03F1/42 ,  H03F3/45748 ,  H02M1/0009 ,  H03F2203/45084

Abstract: A current sensing topology uses an amplifier with capacitively coupled inputs in feedback to sense the input offset of the amplifier, which can be compensated for during measurement. The amplifier with capacitively coupled inputs in feedback is used to: operate the amplifier in a region where the input common-mode specifications are relaxed, so that the feedback loop gain and/or bandwidth is higher; operate the sensor from the converter input voltage by employing high-PSRR (power supply rejection ratio) regulators to create a local, clean supply voltage, causing less disruption to the power grid in the switch area; sample the difference between the input voltage and the controller supply, and recreate that between the drain voltages of the power and replica switches; and compensate for power delivery network related (PDN-related) changes in the input voltage during current sensing.