公开(公告)号：US20160350180A1

公开(公告)日：2016-12-01

申请号：US14865956

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C11/40 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C29/56008 ,  G11C2029/0411

Abstract: A memory subsystem enables managing error correction information. A memory device internally performs error detection for a range of memory locations, and increments an internal count for each error detected. The memory device includes ECC logic to generate an error result indicating a difference between the internal count and a baseline number of errors preset for the memory device. The memory device can provide the error result to an associated host of the system to expose only a number of errors accumulated without exposing internal errors from prior to incorporation into a system. The memory device can be made capable to generate internal addresses to execute commands received from the memory controller. The memory device can be made capable to reset the counter after a first pass through the memory area in which errors are counted.

Abstract translation: 存储器子系统能够管理纠错信息。 内存设备内部对一系列内存位置执行错误检测，并为检测到的每个错误增加内部计数。 存储器件包括ECC逻辑，用于产生指示内存计数与为存储器件预设的基准线数之间的差异的错误结果。 存储器装置可以向系统的相关联的主机提供错误结果，以仅暴露出许多累积的错误，而不会将内部错误暴露于系统之前。 可以使存储器件能够产生内部地址以执行从存储器控制器接收的命令。 可以使存储器件能够在首次通过其中计数错误的存储区域之后复位计数器。

公开(公告)号：US09286964B2

公开(公告)日：2016-03-15

申请号：US13725800

申请日：2012-12-21

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G11C11/406 ,  G11C11/4076

CPC classification number: G11C11/40618 ,  G06F3/0616 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0646 ,  G06F12/0684 ,  G11C7/1072 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4076

Abstract: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

Abstract translation: 促进存储器设备的操作模式以准备存储器中的行的目标刷新的技术和机制。 在一个实施例中，存储器装置在处于来自存储器控制器的未来命令的模式中执行一个或多个操作，该命令至少部分地实现存储器的第一存储体中的行的目标刷新 设备。 在这样的命令之前，存储器设备从存储器控制器服务另一命令。 在另一个实施例中，服务另一个命令包括存储设备访问存储器设备的第二组，同时存储设备在模式下操作，并且在预期的未来目标行刷新完成之前。

公开(公告)号：US20140177370A1

公开(公告)日：2014-06-26

申请号：US13725800

申请日：2012-12-21

Applicant: INTEL CORPORATION

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G11C11/402

CPC classification number: G11C11/40618 ,  G06F3/0616 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0646 ,  G06F12/0684 ,  G11C7/1072 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4076

Abstract: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

Abstract translation: 促进存储器设备的操作模式以准备存储器中的行的目标刷新的技术和机制。 在一个实施例中，存储器装置在处于来自存储器控制器的未来命令的模式中执行一个或多个操作，该命令至少部分地实现存储器的第一存储体中的行的目标刷新 设备。 在这样的命令之前，存储器设备从存储器控制器服务另一命令。 在另一个实施例中，服务另一个命令包括存储设备访问存储器设备的第二组，同时存储设备在模式下操作，并且在预期的未来目标行刷新完成之前。

公开(公告)号：US10810079B2

公开(公告)日：2020-10-20

申请号：US16178528

申请日：2018-11-01

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C29/42 ,  H03M13/09 ,  H03M13/00 ,  G11C11/401

Abstract: An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

公开(公告)号：US10459809B2

公开(公告)日：2019-10-29

申请号：US15640182

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Hussein Alameer ,  Uksong Kang ,  Kjersten E. Criss ,  Rajat Agarwal ,  Wei Wu ,  John B. Halbert

IPC: G11C5/02 ,  G06F11/16 ,  G06F11/10 ,  G11C5/04 ,  G11C7/10 ,  G11C29/42 ,  G11C29/52 ,  G11C29/00 ,  G11C7/24 ,  H01L25/065 ,  G11C29/04

Abstract: A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information.

公开(公告)号：US09659626B1

公开(公告)日：2017-05-23

申请号：US14998091

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Kuljit S. Bains ,  John B. Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4096

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096

Abstract: Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.

公开(公告)号：US20170140801A1

公开(公告)日：2017-05-18

申请号：US15360675

申请日：2016-11-23

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Bruce A. Christenson ,  Kuljit S. Bains

IPC: G11C7/10 ,  G06F13/16

CPC classification number: G11C7/1072 ,  G06F13/1668 ,  G06F13/1689 ,  G06F21/79 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1063 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4094 ,  Y02D10/14

Abstract: Techniques and mechanisms for exchanging information between a memory controller and a memory device. In an embodiment, a memory controller receives information indicating for a memory device a threshold number of pending consolidated activation commands to access that memory device. The threshold number indicated by the information is less than a theoretical maximum number of pending consolidated activation commands, the theoretical maximum number defined based on timing parameters of the memory device. In another embodiment, the memory controller limits communication of consolidated activation commands to the memory device based on the information indicating the threshold number.

公开(公告)号：US20170063394A1

公开(公告)日：2017-03-02

申请号：US14998142

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains ,  Kjersten E. Criss

IPC: H03M13/09 ,  H03M13/00

CPC classification number: G06F11/1048 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/401 ,  G11C29/42 ,  G11C29/52 ,  H03M13/095 ,  H03M13/6566

Abstract: In a system where a memory device performs on-die ECC, the ECC operates on N-bit data words as two (N/2)-bit segments, with a code matrix having a corresponding N codes that can be operated on as a first portion of (N/2) codes and a second portion of (N/2) codes to compute first and second error checks for first and second (N/2)-bit segments of the data word, respectively. In the code matrix, a bitwise XOR of any two codes in the first portion of the code matrix or any two codes in the second portion of the code matrix results in a code that is either not in the code matrix or is in the other portion of the code matrix. Thus, a miscorrected double bit error in one portion causes a bit to be toggled in the other portion instead of creating a triple bit error.

Abstract translation: 在存储器件执行管芯ECC的系统中，ECC对N位数据字进行二（N / 2）位段的操作，其中码矩阵具有对应的N个代码，可以作为第一 （N / 2）码的一部分和（N / 2）码的第二部分，分别计算数据字的第一和第二（N / 2）位段的第一和第二错误检查。 在代码矩阵中，代码矩阵的第一部分中的任何两个代码的按位XOR或代码矩阵的第二部分中的任何两个代码产生不在代码矩阵中的代码，或者在另一部分中 的代码矩阵。 因此，一个部分中的错误的双位错误导致在另一部分中切换位而不是产生三位错误。

公开(公告)号：US20160276015A1

公开(公告)日：2016-09-22

申请号：US15170606

申请日：2016-06-01

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert

IPC: G11C11/4078 ,  G11C11/406

CPC classification number: G11C11/4078 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/408 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/0409

Abstract: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

Abstract translation: 存储器子系统的检测逻辑获得存储器设备的阈值，该存储器设备指示在时间窗口内的数量的访问，导致物理上相邻的行上的数据损坏风险。 检测逻辑从存储器件的配置信息的寄存器获得阈值，并且可以是存储器件本身的寄存器和/或可以是存储器件所属的存储器模块的配置存储设备的条目 。 检测逻辑确定对存储器件的行的访问次数是否超过阈值。 响应于检测到的访问次数超过阈值，检测逻辑可以产生触发以使存储器件执行针对物理上相邻的受害者行的刷新。

公开(公告)号：US20160254036A1

公开(公告)日：2016-09-01

申请号：US14926860

申请日：2015-10-29

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert

IPC: G11C7/10 ,  G06F13/42

CPC classification number: G06F3/0659 ,  G06F3/0605 ,  G06F3/0683 ,  G06F13/4022 ,  G06F13/4282 ,  G06F13/4295 ,  G06F15/7807 ,  G11C7/1003 ,  G11C7/1021 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4097 ,  Y02D10/14 ,  Y02D10/151

Abstract: Flexible command addressing for memory. An embodiment of a memory device includes a dynamic random-access memory (DRAM); and a system element coupled with the DRAM, the system element including a memory controller for control of the DRAM. The DRAM includes a memory bank, a bus, the bus including a plurality of pins for the receipt of commands, and a logic, wherein the logic provides for shared operation of the bus for a first type of command and a second type of command received on a first set of pins.

Abstract translation: 内存灵活的命令寻址。 存储器件的实施例包括动态随机存取存储器（DRAM）; 以及与DRAM耦合的系统元件，所述系统元件包括用于控制DRAM的存储器控​​制器。 DRAM包括存储体，总线，总线包括用于接收命令的多个引脚和逻辑，其中逻辑提供用于第一类型的命令的总线的共享操作和接收的第二类型的命令 在第一组引脚上。