公开(公告)号：US08825989B2

公开(公告)日：2014-09-02

申请号：US14063789

申请日：2013-10-25

Applicant: Intel Corporation

Inventor： Avinash Sodani ,  Stephan Jourdan ,  Alexandre Farcy ,  Per Hammarlund

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/45504

Abstract: A technique to perform three-source instructions. At least one embodiment of the invention relates to converting a three-source instruction into at least two instructions identifying no more than two source values.

Abstract translation: 一种执行三源指令的技术。 本发明的至少一个实施例涉及将三源指令转换成标识不超过两个源值的至少两个指令。

公开(公告)号：US10452403B2

公开(公告)日：2019-10-22

申请号：US14866875

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Hong Wang ,  John P. Shen ,  Edward T. Grochowski ,  Richard A. Hankins ,  Gautham N. Chinya ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju V. Patel ,  James P Held

IPC: G06F9/455 ,  G06F9/38 ,  G06F9/30 ,  G06F9/48

Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

公开(公告)号：US10089263B2

公开(公告)日：2018-10-02

申请号：US15118501

申请日：2014-03-24

Applicant: INTEL CORPORATION ,  Thiam Wah Loh ,  Gautham N. Chinya ,  Per Hammarlund ,  Reza Fortas ,  Hong Wang ,  Huajin Sun

Inventor： Thiam Wah Loh ,  Gautham N. Chinya ,  Per Hammarlund ,  Reza Fortas ,  Hong Wang ,  Huajin Sun

IPC: G06F13/24

Abstract: A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time, unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time, the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.

公开(公告)号：US09910796B2

公开(公告)日：2018-03-06

申请号：US13844343

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Hong Wang ,  Per Hammarlund ,  Xiang Zou ,  John P. Shen ,  Xinmin Tian ,  Milind Girkar ,  Perry H. Wang ,  Piyush N. Desai

IPC: G06F9/38 ,  G06F13/24 ,  G06F9/30 ,  G06F9/48 ,  G06F11/34

CPC classification number: G06F13/24 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/4843 ,  G06F11/3024 ,  G06F11/348 ,  G06F12/0875 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/452

Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

公开(公告)号：US09733937B2

公开(公告)日：2017-08-15

申请号：US13843305

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Bratin Saha ,  Matthew C. Merten ,  Per Hammarlund

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52

CPC classification number: G06F9/30021 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3857 ,  G06F9/526 ,  G06F2209/521

Abstract: A method, apparatus, and system are provided for performing compare and exchange operations using a sleep-wakeup mechanism. According to one embodiment, an instruction at a processor is executed to help acquire a lock on behalf of the processor. If the lock is unavailable to be acquired by the processor, the instruction is put to sleep until an event has occurred.

公开(公告)号：US09588771B2

公开(公告)日：2017-03-07

申请号：US13791298

申请日：2013-03-08

Applicant: Intel Corporation

Inventor： Hong Wang ,  John Shen ,  Hong Jiang ,  Richard Hankins ,  Per Hammarlund ,  Dion Rodgers ,  Gautham Chinya ,  Baiju Patel ,  Shiv Kaushik ,  Bryant Bigbee ,  Gad Sheaffer ,  Yoav Talgam ,  Yuval Yosef ,  James P. Held

IPC: G06F9/38 ,  G06F9/30 ,  G06T1/20

CPC classification number: G06F9/30145 ,  G06F9/30 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3879 ,  G06T1/20

Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在加速器和与其耦合的指令定序器之间直接通信的方法，其中加速器相对于指令定序器是异质资源。 可以使用接口来提供这些资源之间的通信。 通过这种通信机制，用户级应用可以直接与加速器进行通信，而无需操作系统支持。 此外，指令定序器和加速器可以并行地执行操作。 描述和要求保护其他实施例。

公开(公告)号：US09459874B2

公开(公告)日：2016-10-04

申请号：US14541933

申请日：2014-11-14

Applicant: Intel Corporation

Inventor： Hong Wang ,  John Shen ,  Hong Jiang ,  Richard Hankins ,  Per Hammarlund ,  Dion Rodgers ,  Gautham Chinya ,  Baiju Patel ,  Shiv Kaushik ,  Bryant Bigbee ,  Gad Sheaffer ,  Yoav Talgam ,  Yuval Yosef ,  James P. Held

IPC: G06F9/38 ,  G06F9/30 ,  G06T1/20

CPC classification number: G06F9/30145 ,  G06F9/30 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3879 ,  G06T1/20

Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在加速器和与其耦合的指令定序器之间直接通信的方法，其中加速器相对于指令定序器是异质资源。 可以使用接口来提供这些资源之间的通信。 通过这种通信机制，用户级应用可以直接与加速器进行通信，而无需操作系统支持。 此外，指令定序器和加速器可以并行地执行操作。 描述和要求保护其他实施例。

公开(公告)号：US20160095060A1

公开(公告)日：2016-03-31

申请号：US14498572

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Parmoon Seddighrad ,  Ashoke Ravi ,  Georgios Palaskas ,  Per Hammarlund

IPC: H04W52/02 ,  H04W4/00

CPC classification number: H04W52/0225 ,  H04W4/80 ,  Y02D70/00 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164 ,  Y02D70/166 ,  Y02D70/168 ,  Y02D70/21 ,  Y02D70/22 ,  Y02D70/26

Abstract: The disclosure relates to a method, apparatus and system to provide an integrated HUB for communicating with wearable devices. The exemplary devices include an Offloading engine to communicate directly with the wearable devices at reduced power and with relaxed radio specification requirement. In one embodiment, the disclosure relates to a system having one or more antennas; a platform radio to communicate with the one or more antennas; a platform processor to communicate with the platform radio; and a first logic to combine incoming data from one or more wearable sensors, the first logic configured to fuse incoming data from the one or more wearable sensors and to determine whether to awaken the host platform.

Abstract translation: 本公开涉及提供用于与可穿戴设备通信的集成HUB的方法，装置和系统。 示例性设备包括卸载引擎，以降低的功率与可穿戴设备直接通信，并且具有放松的无线电规范要求。 在一个实施例中，本公开涉及具有一个或多个天线的系统; 与所述一个或多个天线通信的平台无线电台; 与平台无线电通信的平台处理器; 以及第一逻辑，用于组合来自一个或多个可佩戴传感器的输入数据，所述第一逻辑被配置为将来自所述一个或多个可佩戴传感器的输入数据进行融合并确定是否唤醒所述主机平台。

公开(公告)号：US09164764B2

公开(公告)日：2015-10-20

申请号：US14286536

申请日：2014-05-23

Applicant: INTEL CORPORATION

Inventor： Ethan Schuchman ,  Hong Wang ,  Chris Weaver ,  Belliappa M. Kuttanna ,  Asit Mallick ,  Vivek K. De ,  Per Hammarlund

IPC: G06F9/30 ,  G06F1/32 ,  G06F9/46

CPC classification number: G06F9/30083 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3246 ,  G06F1/3265 ,  G06F1/3268 ,  G06F1/3296 ,  G06F9/30043 ,  G06F9/30105 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/461 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/153 ,  Y02D10/154 ,  Y02D10/172 ,  Y02D50/20

Abstract: Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.

Abstract translation: 公开了用于降低处理器开关操作功耗的方法和装置。 一个或多个实施例可以包括指定要参与寄存器或状态存储操作的寄存器或状态存储元件的子集，执行寄存器或状态存储操作，以及执行开关操作。 这些实施例可以通过仅指定寄存器或状态存储元件的子集来最小化与备用操作相关的寄存器或状态存储元件的数量，其可能涉及明显少于处理器的寄存器或状态存储器或元件的总数量。 切换操作可以从一种模式切换到另一种模式，例如转换到睡眠模式，上下文切换或各种类型的指令的执行。