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公开(公告)号：US09577060B2
公开(公告)日：2017-02-21
申请号：US14778726
申请日：2013-06-29
Applicant: Intel Corporation
Inventor： Raseong Kim , Ian A. Young
IPC: H03H9/24 , H01L29/423 , H03H9/02 , H01L27/088 , H03H9/17
CPC classification number: H01L29/42356 , H01L27/0886 , H03H9/02259 , H03H9/17 , H03H9/2405 , H03H2009/02314
Abstract: An embodiment includes a first nonplanar transistor including a first fin that includes first source and drain nodes, and a first channel between the first source and drain nodes; a second nonplanar transistor including a second fin that includes second source and drain nodes, and a second channel between the second source and drain nodes; a nonplanar gate on the first fin between the first source and drain nodes and on the second fin between the second source and drain nodes; and first insulation included between the gate and the first fin and second insulation between the gate and the second fin; wherein the gate mechanically resonates at a first frequency when at least one of the gate and the first fin is actuated with alternating current (AC) to produce periodic forces on the gate. Other embodiments are described herein.
Abstract translation: 一个实施例包括第一非平面晶体管，其包括包括第一源极和漏极节点的第一鳍片，以及在第一源极和漏极节点之间的第一沟道; 第二非平面晶体管，包括包括第二源极和漏极节点的第二鳍片，以及在所述第二源极和漏极节点之间的第二沟道; 位于第一源极和漏极节点之间的第一鳍片上的非平面栅极和在第二源极和漏极节点之间的第二鳍片上; 并且所述栅极和所述第一鳍片之间包括第一绝缘体，并且所述栅极和所述第二鳍片之间的第二绝缘体; 其中当所述栅极和所述第一鳍中的至少一个用交流电（AC）致动以在所述栅极上产生周期性力时，所述栅极以第一频率机械谐振。 本文描述了其它实施例。
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公开(公告)号：US20250008852A1
公开(公告)日：2025-01-02
申请号：US18346212
申请日：2023-07-01
Applicant: Intel Corporation
Inventor： Punyashloka Debashis , Dominique A. Adams , Gauri Auluck , Scott B. Clendenning , Arnab Sen Gupta , Brandon Holybee , Raseong Kim , Matthew V. Metz , Kevin P. O'Brien , John J. Plombon , Marko Radosavljevic , Carly Rogan , Hojoon Ryu , Rachel A. Steinhardt , Tristan A. Tronic , I-Cheng Tung , Ian Alexander Young , Dmitri Evgenievich Nikonov
Abstract: A two-terminal ferroelectric perovskite diode comprises a region of ferroelectric perovskite material positioned adjacent to a region of n-type doped perovskite semiconductor material. Asserting a positive voltage across the diode can cause the polarization of the ferroelectric perovskite material to be set in a first direction that causes the diode to be placed in a low resistance state due to the formation of an accumulation region in the perovskite semiconductor material at the ferroelectric perovskite-perovskite semiconductor boundary. Asserting a negative voltage across the diode can cause the polarization of the ferroelectric perovskite material to be set in a second direction that causes the diode to be placed in a high resistance state due to the formation of a depletion region in the perovskite semiconductor material at the ferroelectric perovskite-perovskite semiconductor material. These non-volatile low and high resistance states enable the diode to be used as a non-volatile memory element.
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公开(公告)号：US20230317847A1
公开(公告)日：2023-10-05
申请号：US17711665
申请日：2022-04-01
Applicant: Intel Corporation
Inventor： Hai Li , Ian Alexander Young , Dmitri Evgenievich Nikonov , Julien Sebot , Raseong Kim , Chia-Ching Lin , Punyashloka Debashis
CPC classification number: H01L29/78391 , H01L43/10
Abstract: Technologies for majority gates are disclosed. In one embodiment, a ferroelectric layer has three inputs and an output adjacent a surface of the ferroelectric. When a voltage is applied to each input, the inputs and a ground plane below the ferroelectric layer form a capacitor. The ferroelectric layer becomes polarized based on the applied voltages at the inputs. The portion of the ferroelectric layer near the output becomes polarized in the direction of polarization of the majority of the inputs. The output voltage then reflects the majority voltage of the inputs.
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公开(公告)号：US11637191B2
公开(公告)日：2023-04-25
申请号：US16238420
申请日：2019-01-02
Applicant: Intel Corporation
Inventor： Tanay Gosavi , Chia-ching Lin , Raseong Kim , Ashish Verma Penumatcha , Uygar Avci , Ian Young
IPC: H01L29/51 , H01L29/78 , H01L27/088 , H03H9/17 , H01L29/423
Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.
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公开(公告)号：US20200212194A1
公开(公告)日：2020-07-02
申请号：US16238420
申请日：2019-01-02
Applicant: Intel Corporation
Inventor： Tanay Gosavi , Chia-ching Lin , Raseong Kim , Ashish Verma Penumatcha , Uygar Avci , Ian Young
IPC: H01L29/51 , H01L27/088 , H01L29/423 , H03H9/17 , H01L29/78
Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.
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Patent Agency Ranking
公开(公告)号：US09374162B2
公开(公告)日：2016-06-21
申请号：US13719884
申请日：2012-12-19
Applicant: Intel Corporation
Inventor： Robert L. Sankman , Johanna M. Swan , Dmitri E. Nikonov , Raseong Kim
CPC classification number: H04B10/2504 , G02B6/43 , H04B10/801
Abstract: Described herein are technologies related to a semiconductor package that is installed in a portable device for data communications. More particularly, the semiconductor package that contains a memory, a digital logic chip, and an optical port in a single module or mold is described.
Abstract translation: 这里描述了与安装在用于数据通信的便携式设备中的半导体封装有关的技术。 更具体地，描述了在单个模块或模具中包含存储器，数字逻辑芯片和光学端口的半导体封装。
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公开(公告)号：US08963135B2
公开(公告)日：2015-02-24
申请号：US13690407
申请日：2012-11-30
Applicant: Intel Corporation
Inventor： Dmitri E. Nikonov , Robert L. Sankman , Raseong Kim , Jin Pan
CPC classification number: H05K3/4644 , B29C64/00 , B32B27/06 , B32B2457/00 , B33Y50/02 , B33Y70/00 , B33Y80/00 , H01L27/0688 , H01L27/281 , H01L51/0004 , H05K1/00
Abstract: Three dimensional integrated circuits including semiconductive organic materials are described. In some embodiments, the three dimensional integrated circuits include one or more electronic components that include a semiconductive region formed of one or more semiconductive organic materials. The electronic components of the three dimensional integrated circuits may also include insulating regions formed from organic insulating materials, and conductive regions form from conductive materials. The three dimensional integrated circuits may be formed by an additive manufacturing process such as three dimensional printing. Apparatus and methods for producing and testing three dimensional integrated circuits are also described.
Abstract translation: 描述了包括半导体有机材料在内的三维集成电路。 在一些实施例中，三维集成电路包括一个或多个电子部件，其包括由一个或多个半导体有机材料形成的半导体区域。 三维集成电路的电子部件还可以包括由有机绝缘材料形成的绝缘区域，并且由导电材料形成导电区域。 三维集成电路可以通过诸如三维印刷之类的添加剂制造工艺形成。 还描述了用于生产和测试三维集成电路的装置和方法。
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公开(公告)号：US20250006840A1
公开(公告)日：2025-01-02
申请号：US18344022
申请日：2023-06-29
Applicant: INTEL CORPORATION
Inventor： Rachel A. Steinhardt , Kevin P. O'Brien , Dmitri Evgenievich Nikonov , John J. Plombon , Tristan A. Tronic , Ian Alexander Young , Matthew V. Metz , Marko Radosavljevic , Carly Rogan , Brandon Holybee , Raseong Kim , Punyashloka Debashis , Dominique A. Adams , I-Cheng Tung , Arnab Sen Gupta , Gauri Auluck , Scott B. Clendenning , Pratyush P. Buragohain , Hai Li
IPC: H01L29/78 , H01L29/76 , H01L29/786
Abstract: In one embodiment, a negative capacitance transistor device includes a perovskite semiconductor material layer with first and second perovskite conductors on opposite ends of the perovskite semiconductor material layer. The device further includes a dielectric material layer on the perovskite semiconductor material layer between the first and second perovskite conductors, a perovskite ferroelectric material layer on the dielectric material layer, and a third perovskite conductor on the perovskite ferroelectric material layer.
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公开(公告)号：US20250006791A1
公开(公告)日：2025-01-02
申请号：US18346227
申请日：2023-07-01
Applicant: Intel Corporation
Inventor： Rachel A. Steinhardt , Kevin P. O'Brien , Dominique A. Adams , Gauri Auluck , Pratyush P. Buragohain , Scott B. Clendenning , Punyashloka Debashis , Arnab Sen Gupta , Brandon Holybee , Raseong Kim , Matthew V. Metz , John J. Plombon , Marko Radosavljevic , Carly Rogan , Tristan A. Tronic , I-Cheng Tung , Ian Alexander Young , Dmitri Evgenievich Nikonov
IPC: H01L29/08 , H01L29/06 , H01L29/12 , H01L29/423 , H01L29/51 , H01L29/66 , H01L29/775 , H01L29/78 , H01L29/786
Abstract: Perovskite oxide field effect transistors comprise perovskite oxide materials for the channel, source, drain, and gate oxide regions. The source and drain regions are doped with a higher concentration of n-type or p-type dopants (depending on whether the transistor is an n-type or p-type transistor) than the dopant concentration in the channel region to minimize Schottky barrier height between the source and drain regions and the source and drain metal contact and contact resistance.
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公开(公告)号：US20240105810A1
公开(公告)日：2024-03-28
申请号：US17952161
申请日：2022-09-23
Applicant: Intel Corporation
Inventor： Rachel A. Steinhardt , Ian Alexander Young , Dmitri Evgenievich Nikonov , Marko Radosavljevic , Matthew V. Metz , John J. Plombon , Raseong Kim , Kevin P. O'Brien , Scott B. Clendenning , Tristan A. Tronic , Dominique A. Adams , Carly Rogan , Arnab Sen Gupta , Brandon Holybee , Punyashloka Debashis , I-Cheng Tung , Gauri Auluck
CPC classification number: H01L29/516 , H01L29/6684 , H01L29/66969 , H01L29/7831
Abstract: In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.
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