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公开(公告)号：US20210407168A1
公开(公告)日：2021-12-30
申请号：US17070095
申请日：2020-10-14
Applicant: Intel Corporation
Inventor： Vivek De , Ram Krishnamurthy , Amit Agarwal , Steven Hsu , Monodeep Kar
Abstract: A method comprising: dividing a 3D space into a voxel grid comprising a plurality of voxels; associating a plurality of distance values with the plurality of voxels, each distance value based on a distance to a boundary of an object; selecting an approximate interpolation mode for stepping a ray through a first one or more voxels of the 3D space responsive to the first one or more voxels having distance values greater than a threshold; and detecting the ray reaching a second one or more voxels having distance values less than the first threshold; and responsively selecting a precise interpolation mode for stepping the ray through the second one or more voxels.
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公开(公告)号：US20210407039A1
公开(公告)日：2021-12-30
申请号：US16917791
申请日：2020-06-30
Applicant: Intel Corporation
Inventor： Vivek De , Ram Krishnamurthy , Amit Agarwal , Steven Hsu , Monodeep Kar
Abstract: A method comprising: dividing a 3D space into a voxel grid comprising a plurality of voxels; associating a plurality of distance values with the plurality of voxels, each distance value based on a distance to a boundary of an object; selecting an approximate interpolation mode for stepping a ray through a first one or more voxels of the 3D space responsive to the first one or more voxels having distance values greater than a threshold; and detecting the ray reaching a second one or more voxels having distance values less than the first threshold; and responsively selecting a precise interpolation mode for stepping the ray through the second one or more voxels.
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公开(公告)号：US10784865B1
公开(公告)日：2020-09-22
申请号：US16413110
申请日：2019-05-15
Applicant: Intel Corporation
Inventor： Pascal Meinerzhagen , Vivek De , Muhammad Khellah
IPC: H03K19/003 , H03K5/14 , G06F1/10 , H03K5/135
Abstract: A minimum delay error apparatus such as a minimum delay error detection, prediction, correction, repair, prevention, and/or avoidance apparatus includes a minimum delay path replica circuit. The minimum delay path replica circuit can detect or predict, and subsequently can correct or avoid, minimum delay errors in data paths of digital circuits using pulsed latches.
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14.发明授权公开(公告)号：US09577641B2
公开(公告)日：2017-02-21
申请号：US15016260
申请日：2016-02-04
Applicant: Intel Corporation
Inventor： Arijit Raychowdhury , James W. Tschanz , Vivek De
IPC: H03K19/177 , G11C11/16
CPC classification number: H03K19/17728 , G11C11/16 , H03K19/177
Abstract: Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory.
Abstract translation: 这里公开了使用基于高密度旋转转矩（STT）的存储器元件的半导体器件阵列，诸如现场可编程门阵列（FPGA）和复数可编程逻辑阵列（CPLAs）。 基于STT的存储器元件可以是独立的FPGA / CPLAs，或者可以嵌入在微处理器和/或数字信号处理（DSP）片上系统（SoC）中，以提供设计灵活性，以实现低功率，可扩展，安全 和可重构硬件架构。 由于配置存储在FPGA / CPLA裸片本身，所以每次在外部存储器上加载配置的需求都将在设备通电时被消除。 除了即时启动，消除配置I / O流量导致节电和可能的引脚数减少。 通过消除将配置数据存储在外部存储器中的需要，安全性大大提高。
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公开(公告)号：US20220075400A1
公开(公告)日：2022-03-10
申请号：US17528241
申请日：2021-11-17
Applicant: Intel Corporation
Inventor： Sriram R. Vangal , Jayanth Mallanayakanahalli Devaraju , Vivek De , Robert Milstrey , Stephen H. Gunther
IPC: G05F1/46 , G06F16/901 , G06F1/3203 , G06F1/28
Abstract: In one embodiment, a processor includes a minimum energy point (MEP) controller to: generate a change in thermal tracking information, based at least in part on prior and current thermal information; generate a change in activity tracking information, based at least in part on prior activity information and current activity information; and determine a MEP performance state based at least in part on the change in thermal tracking information and the change in activity tracking information. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US11231731B2
公开(公告)日：2022-01-25
申请号：US16455929
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Sriram R. Vangal , Jayanth Mallanayakanahalli Devaraju , Vivek De , Robert Milstrey , Stephen H. Gunther
IPC: G06F1/3203 , G06F1/28 , G05F1/46 , G06F16/901 , G06F16/90
Abstract: In one embodiment, a processor includes a minimum energy point (MEP) controller to: generate a change in thermal tracking information, based at least in part on prior and current thermal information; generate a change in activity tracking information, based at least in part on prior activity information and current activity information; and determine a MEP performance state based at least in part on the change in thermal tracking information and the change in activity tracking information. Other embodiments are described and claimed.
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17.发明申请公开(公告)号：US20210103308A1
公开(公告)日：2021-04-08
申请号：US17100603
申请日：2020-11-20
Applicant: Intel Corporation
Inventor： Xiaosen Liu , Harish Krishnamurthy , Krishnan Ravichandran , Vivek De , Scott Chiu , Claudia Patricia Barrera Gonzalez , Jing Han , Rajasekhara Madhusudan Narayana Bhatla
Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.
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公开(公告)号：US20200312404A1
公开(公告)日：2020-10-01
申请号：US16417538
申请日：2019-05-20
Applicant: Intel Corporation
Inventor： Vivek De , Sanu Mathew , Sudhir Satpathy , Vikram Suresh , Raghavan Kumar
IPC: G11C11/419 , H04L9/32
Abstract: Techniques and mechanisms for changing a consistency with which a cell circuit (“cell”) settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCI) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCI stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.
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公开(公告)号：US10298117B2
公开(公告)日：2019-05-21
申请号：US15638643
申请日：2017-06-30
Applicant: INTEL CORPORATION
Inventor： Harish Krishnamurthy , Khondker Ahmed , Vivek De , Nachiket Desai , Suhwan Kim , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram Vangal
Abstract: Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.
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公开(公告)号：US20180375433A1
公开(公告)日：2018-12-27
申请号：US15632086
申请日：2017-06-23
Applicant: INTEL CORPORATION
Inventor： Khondker Ahmed , Vivek De , Nachiket Desai , Suhwan Kim , Harish Krishnamurthy , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram Vangal
CPC classification number: H02M3/1582 , G05F1/67 , H02M1/08 , H02M2001/0003 , H02M2001/0009 , H02M2001/0025
Abstract: Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.
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