公开(公告)号：US20190097055A1

公开(公告)日：2019-03-28

申请号：US16081572

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： GILBERT DEWEY ,  TAHIR GHANI ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  MATTHEW V. METZ ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8238

CPC classification number: H01L29/7853 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/4236 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818

Abstract: Techniques are disclosed for forming a beaded fin transistor. As will be apparent in light of this disclosure, a transistor including a beaded fin configuration may be formed by starting with a multilayer finned structure, and then selectively etching one or more of the layers to form at least one necked (or relatively narrower) portion, thereby forming a beaded fin structure. The beaded fin transistor configuration has improved gate control over a finned transistor configuration having the same top down area or footprint, because the necked/narrower portions increase gate surface area as compared to a non-necked finned structure, such as finned structures used in finFET devices. Further, because the beaded fin structure remains intact (e.g., as compared to a gate-all-around (GAA) transistor configuration where nanowires are separated from each other), the parasitic capacitance problems caused by GAA transistor configurations are mitigated or eliminated.

公开(公告)号：US20190043993A1

公开(公告)日：2019-02-07

申请号：US16076550

申请日：2016-03-11

Applicant: INTEL CORPORATION

Inventor： CHANDRA S. MOHAPATRA ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  WILLY RACHMADY ,  GILBERT DEWEY ,  TAHIR GHANI ,  JACK T. KAVALIEROS

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8252

Abstract: Techniques are disclosed for forming transistors including one or more group III-V semiconductor material nanowires using sacrificial group IV semiconductor material layers. In some cases, the transistors may include a gate-all-around (GAA) configuration. In some cases, the techniques may include forming a replacement fin stack that includes group III-V material layer (such as indium gallium arsenide, indium arsenide, or indium antimonide) formed on a group IV material buffer layer (such as silicon, germanium, or silicon germanium), such that the group IV buffer layer can be later removed using a selective etch process to leave the group III-V material for use as a nanowire in a transistor channel. In some such cases, the group III-V material layer may be grown pseudomorphically to the underlying group IV material, so as to not form misfit dislocations. The techniques may be used to form transistors including any number of nanowires.

公开(公告)号：US20180374928A1

公开(公告)日：2018-12-27

申请号：US15776752

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： GILBERT DEWEY ,  ASHISH AGRAWAL ,  BENJAMIN CHU-KUNG ,  VAN H. LE ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  RAFAEL RIOS

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/513 ,  H01L29/16 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: Embodiments of the present disclosure describe semiconductor devices comprised of a semiconductor substrate with a metal oxide semiconductor field effect transistor having a channel including germanium or silicon-germanium, where a dielectric layer is coupled to the channel. The dielectric layer may include a metal oxide and at least one additional element, where the at least one additional element may increase a band gap of the dielectric layer. A gate electrode may be coupled to the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20180047839A1

公开(公告)日：2018-02-15

申请号：US15790907

申请日：2017-10-23

Applicant: INTEL CORPORATION

Inventor： RAVI PILLARISETTY ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  UDAY SHAH ,  BENJAMIN CHU-KUNG ,  MARKO RADOSAVLJEVIC ,  NILOY MUKHERJEE ,  GILBERT DEWEY ,  BEEN Y. JIN ,  ROBERT S. CHAU

IPC: H01L29/775 ,  B82Y10/00 ,  H01L29/778 ,  H01L29/66 ,  H01L29/267 ,  H01L29/15 ,  H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L21/76 ,  H01L29/51 ,  H01L29/165

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7782 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

公开(公告)号：US20160172472A1

公开(公告)日：2016-06-16

申请号：US15043935

申请日：2016-02-15

Applicant: INTEL CORPORATION

Inventor： RAVI PILLARISETTY ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  UDAY SHAH ,  BENJAMIN CHU-KUNG ,  MARKO RADOSAVLJEVIC ,  NILOY MUKHERJEE ,  GILBERT DEWEY ,  BEEN Y. JIN ,  ROBERT S. CHAU

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/78 ,  H01L29/15

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7782 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

Abstract translation: 公开了用于形成非平面锗量子阱结构的技术。 特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。 在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。 在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。

公开(公告)号：US20190115466A1

公开(公告)日：2019-04-18

申请号：US16214946

申请日：2018-12-10

Applicant: INTEL CORPORATION

Inventor： STEPHEN M. CEA ,  ROZA KOTLYAR ,  HAROLD W. KENNEL ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  WILLY RACHMADY ,  TAHIR GHANI

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/04 ,  H01L29/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

公开(公告)号：US20180337235A1

公开(公告)日：2018-11-22

申请号：US15776996

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： WILLY RACHMADY ,  MATTHEW V. METZ ,  GILBERT DEWEY ,  CHANDRA S. MOHAPATRA ,  NADIA M. RAHHAL-ORABI ,  Jack T. KAVALIEROS ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L29/10 ,  H01L29/205 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: Embodiments of the present disclosure describe a semiconductor multi-gate transistor having a semi-conductor fin extending from a substrate and including a sub-fin region and an active region. The subfin region may include a dielectric material region under the gate to provide improved isolation. The dielectric material region may be formed during a replacement gate process by replacing a portion of a sub-fin region under the gate with the dielectric material region, followed by fabrication of a replacement gate structure. The sub-fin region may be comprised of group III-V semiconductor materials in various combinations and concentrations. The active region may be comprised of a different group III-V semiconductor material. The dielectric material region may be comprised of amorphous silicon. Other embodiments may be described and/or claimed.

公开(公告)号：US20180323310A1

公开(公告)日：2018-11-08

申请号：US15529432

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： HAROLD W. KENNEL ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  GILBERT DEWEY ,  CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  JACK T. KAVALIEROS ,  TAHIR GHANI

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/78 ,  H01L29/778 ,  H01L27/06

CPC classification number: H01L29/78681 ,  H01L27/0605 ,  H01L29/1054 ,  H01L29/7783 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices including a subfin including a first III-V semiconductor alloy and a channel including a second III-V semiconductor alloy are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V semiconductor alloy is deposited on the substrate within the trench and the second III-V semiconductor alloy is epitaxially grown on the first III-V semiconductor alloy. In some embodiments, a conduction band offset between the first III-V semiconductor alloy and the second III-V semiconductor alloy is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.

公开(公告)号：US20170358645A1

公开(公告)日：2017-12-14

申请号：US15525269

申请日：2014-12-26

Applicant: INTEL CORPORATION

Inventor： GILBERT DEWEY ,  MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  TAHIR GHANI ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA ,  SANAZ K. GARDNER ,  MARKO RADOSAVLJEVIC ,  GLENN A. GLASS

IPC: H01L29/06 ,  H01L29/12 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L29/78 ,  H01L29/775 ,  H01L21/306 ,  H01L21/02 ,  H01L29/20 ,  H01L29/161 ,  H01L29/04

CPC classification number: H01L29/0673 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/7605 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/122 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66469 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.

公开(公告)号：US20170345900A1

公开(公告)日：2017-11-30

申请号：US15527221

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： HAROLD W. KENNEL ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  GILBERT DEWEY ,  CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  JACK T. KAVALIEROS ,  TAHIR GHANI

IPC: H01L29/205 ,  H01L21/02 ,  H01L21/18

CPC classification number: H01L29/205 ,  H01L21/02455 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/182 ,  H01L21/185

Abstract: Semiconductor devices including a subfin including a first III-V compound semiconductor and a channel including a second III-V compound semiconductor are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V compound semiconductor is deposited on the substrate within the trench and the second III-V compound semiconductor is epitaxially grown on the first III-V compound semiconductor. In some embodiments, a conduction band offset between the first III-V compound semiconductor and the second III-V compound semiconductor is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.