公开(公告)号：US20220196914A1

公开(公告)日：2022-06-23

申请号：US17131678

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Hiroki TANAKA ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Bai NIE ,  Haobo CHEN ,  Zhichao ZHANG ,  Sai VADLAMANI ,  Aleksandar ALEKSOV

IPC: G02B6/12 ,  H01L23/48 ,  G02B6/02 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such structures. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, and a second die over the package substrate. In an embodiment, the electronic package further comprises an optical waveguide on the package substrate. In an embodiment, a first end of the optical waveguide is below the first die and a second end of the optical waveguide is below the second die. In an embodiment, the optical waveguide communicatively couples the first die to the second die.

公开(公告)号：US20220183177A1

公开(公告)日：2022-06-09

申请号：US17677785

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Zhichao ZHANG ,  Gregorio R. MURTAGIAN ,  Kuang C. LIU ,  Kemal AYGUN

IPC: H05K7/10 ,  H05K1/11 ,  H05K1/02 ,  H01R13/24

Abstract: Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.

公开(公告)号：US20180189214A1

公开(公告)日：2018-07-05

申请号：US15396268

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： James A. MCCALL ,  Zhichao ZHANG ,  Qin LI ,  Xiang LI ,  John R. DREW

IPC: G06F13/40 ,  H01R12/72

CPC classification number: G06F13/4022 ,  G06F13/4068 ,  H01R12/721

Abstract: Devices include a connecting card that may be used in a memory connector. The connecting card may include a substrate including a first substrate region and a second substrate region, a plurality of adjacent signal pathways extending from the first substrate region to the second substrate region, and a capacitor positioned between each of the adjacent signal pathways. Other embodiments are described and claimed.

公开(公告)号：US20250038163A1

公开(公告)日：2025-01-30

申请号：US18917500

申请日：2024-10-16

Applicant: Intel Corporation

Inventor： Zhichao ZHANG ,  Kemal AYGÜN ,  Suresh V. POTHUKUCHI ,  Xiaoqian LI ,  Omkar KARHADE

IPC: H01L25/18 ,  G02B6/42 ,  H01L23/373 ,  H01L23/538 ,  H01L25/00

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to disaggregating co-packaged SOC and photonic integrated circuits on an multichip package. The photonic integrated circuits may also be silicon photonics engines. In embodiments, multiple SOCs and photonic integrated circuits may be electrically coupled, respectively, into modules, with multiple modules then incorporated into an MCP using a stacked die structure. Other embodiments may be described and/or claimed.

公开(公告)号：US20220200178A1

公开(公告)日：2022-06-23

申请号：US17131686

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Feifei CHENG ,  Zhe CHEN ,  Ahmet C. DURGUN ,  Zhichao ZHANG

IPC: H01R12/71 ,  H01R12/70 ,  H01R33/76 ,  H01R13/6594 ,  H01R13/24 ,  H01R13/6585 ,  H01R13/6597

Abstract: In an embodiment, a socket comprises a housing, where the housing is a dielectric material. In an embodiment, a shell passes through a thickness of the, where the shell is conductive. The socket may further comprise a plug within the shell, where the plug is a dielectric material, and where the plug has a bottom surface. In an embodiment, a pin passes through the thickness of the housing within an inner diameter of the shell, where the pin has a first portion with a first diameter and a second portion with a second diameter, and where the pin is conductive. In an embodiment, the socket further comprises a spring around the first portion of the pin, where a first end of the spring presses against the bottom surface, and where a second end of the spring presses against the second portion of the pin.

公开(公告)号：US20210272892A1

公开(公告)日：2021-09-02

申请号：US16804516

申请日：2020-02-28

Applicant: Intel Corporation

Inventor： Zhichao ZHANG ,  Zhe CHEN ,  Srikant NEKKANTY ,  Sriram SRINIVASAN

IPC: H01L23/498 ,  H01L23/58

Abstract: Embodiments include assemblies. An assembly includes a substrate having a first interconnect and a second interconnect. The first interconnect has a first conductive pad and a second conductive pad, and the second interconnect has a third conductive pad and a fourth conductive pad. The assembly includes a socket over the substrate. The socket has a first pin, a second pin, and a base layer with a first pad and a second pad. The first and second pins are vertically over the respective first and second interconnects. The first pad is directly coupled to the first pin and fourth conductive pad, while the second pad is directly coupled to the second pin and second conductive pad. The first pad is positioned partially within a footprint of the third conductive pad, and the second pad is positioned partially within a footprint of the first conductive pad.

公开(公告)号：US20180288868A1

公开(公告)日：2018-10-04

申请号：US15997644

申请日：2018-06-04

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Matthew MANUSHAROW ,  Krishna BHARATH ,  Zhichao ZHANG ,  Yidnekachew S. MEKONNEN ,  Aleksandar ALEKSOV ,  Henning BRAUNISCH ,  Feras EID ,  Javier SOTO

IPC: H05K1/02 ,  H01P3/08 ,  H01P3/02

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

公开(公告)号：US20240421025A1

公开(公告)日：2024-12-19

申请号：US18290289

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Lianchang DU ,  Jeffory L. SMALLEY ,  Srikant NEKKANTY ,  Eric W. BUDDRIUS ,  Yi ZENG ,  Xinjun ZHANG ,  Maoxin YIN ,  Zhichao ZHANG ,  Chen ZHANG ,  Yuehong FAN ,  Mingli ZHOU ,  Guoliang YING ,  Yinglei REN ,  Chong J. ZHAO ,  Jun LU ,  Kai WANG ,  Timothy Glen HANNA ,  Vijaya K. BODDU ,  Mark A. SCHMISSEUR ,  Lijuan FENG

IPC: H01L23/367 ,  H01L23/538 ,  H01L25/065 ,  H01R13/627

Abstract: A semiconductor chip package is described. The semiconductor chip package has a substrate. The substrate has side I/Os on the additional surface area of the substrate. The side I/Os are coupled to I/Os of a semiconductor chip within the semiconductor chip package. A cooling assembly has also been described. The cooling assembly has a passageway to guide a cable to connect to a semiconductor chip's side I/Os that are located between a base of a cooling mass and an electronic circuit board that is between a bolster plate and a back plate and that is coupled to second I/Os of the semiconductor chip through a socket that the semiconductor chip's package is plugged into.

公开(公告)号：US20220199600A1

公开(公告)日：2022-06-23

申请号：US17132976

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Zhichao ZHANG ,  Kemal AYGÜN ,  Suresh V. POTHUKUCHI ,  Xiaoqian LI ,  Omkar KARHADE

IPC: H01L25/18 ,  H01L25/00 ,  G02B6/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to disaggregating co-packaged SOC and photonic integrated circuits on an multichip package. The photonic integrated circuits may also be silicon photonics engines. In embodiments, multiple SOCs and photonic integrated circuits may be electrically coupled, respectively, into modules, with multiple modules then incorporated into an MCP using a stacked die structure. Other embodiments may be described and/or claimed.

公开(公告)号：US20220157706A1

公开(公告)日：2022-05-19

申请号：US17665315

申请日：2022-02-04

Applicant: Intel Corporation

Inventor： Sujit SHARAN ,  Kemal AYGUN ,  Zhiguo QIAN ,  Yidnekachew MEKONNEN ,  Zhichao ZHANG ,  Jianyong XIE

IPC: H01L23/498 ,  H01L23/00

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.