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    Methods for Forming Ferroelectric Phases in Materials and Devices Utilizing the Same
    11.
    发明申请
    Methods for Forming Ferroelectric Phases in Materials and Devices Utilizing the Same 审中-公开
    使用它的材料和器件中形成铁电相的方法

    公开(公告)号：US20160181091A1

    公开(公告)日：2016-06-23

    申请号：US14576853

    申请日：2014-12-19

    Applicant: Intermolecular, Inc.

    Inventor： Sandip Niyogi ,  Sergey Barabash ,  Federico Nardi ,  Dipankar Pramanik

    IPC: H01L21/02

    CPC classification number: H01L29/516

    Abstract: Embodiments provided herein describe systems and methods for forming ferroelectric materials. A trench body may be provided. A trench may be formed in the trench body. A dielectric material and a filler material may be deposited within the trench. The filler material may be heated such that a stress is exerted on the dielectric material before the dielectric material is heated to generate a ferroelectric phase within the dielectric material. A non-contiguous layer may be formed above a substrate. A second layer including a high-k dielectric material may be formed above the first layer. The high-k dielectric material may be heated to generate a ferroelectric phase within the high-k dielectric material.

    Abstract translation: 本文提供的实施例描述了用于形成铁电材料的系统和方法。 可以提供沟槽体。 可以在沟槽体中形成沟槽。 介电材料和填充材料可以沉积在沟槽内。 填充材料可以被加热，使得在介电材料被加热之前在电介质材料上施加应力以在电介质材料内产生铁电相。 可以在衬底之上形成不连续的层。 可以在第一层之上形成包括高k电介质材料的第二层。 可以加热高k介电材料以在高k电介质材料内产生铁电相。

    Capacitors including inner and outer electrodes
    12.
    发明授权
    Capacitors including inner and outer electrodes 有权
    电容器包括内外电极

    公开(公告)号：US09224799B2

    公开(公告)日：2015-12-29

    申请号：US14145117

    申请日：2013-12-31

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Dipankar Pramanik

    IPC: H01L49/02 ,  H01L27/08 ,  H01L29/66 ,  H01L29/94 ,  H01L27/108

    CPC classification number: H01L28/75 ,  H01L27/1085 ,  H01L29/66181 ,  H01L29/94

    Abstract: Provided are capacitor stacks for use in integrated circuits and methods of fabricating these stacks. A capacitor stack includes a dielectric layer and one or two inner electrode layers, such as a positive inner electrode layer and a negative inner electrode layer. The inner electrode layers directly interface the dielectric layer. The stack may also include outer electrode layers. The inner electrode layers are either chemically stable or weakly chemically unstable, while in contact with the dielectric layer based on the respective phase diagrams. Furthermore, the electron affinity of the positive inner electrode layer may be less than the electron affinity of the dielectric layer. The sum of the electron affinity and bandgap of the negative inner electrode layer may be less than that of the dielectric layer. In some embodiments, inner electrode layers are formed from heavily doped semiconducting materials, such as gallium arsenide or gallium aluminum arsenide.

    Abstract translation: 提供用于集成电路的电容器堆叠以及制造这些堆叠的方法。 电容器堆叠包括电介质层和一个或两个内部电极层，例如正的内部电极层和负的内部电极层。 内部电极层直接与介电层接触。 堆叠还可以包括外部电极层。 内部电极层是化学稳定的或弱的化学不稳定的，同时基于相应的相图与介电层接触。 此外，正内电极层的电子亲和力可能小于电介质层的电子亲和力。 负的内电极层的电子亲和力和带隙的总和可以小于电介质层的电子亲和力。 在一些实施例中，内部电极层由重掺杂的半导体材料形成，例如砷化镓或砷化镓铝。

    Method of depositing films with narrow-band conductive properties
    14.
    发明授权
    Method of depositing films with narrow-band conductive properties 有权
    沉积窄带导电性能的方法

    公开(公告)号：US09105704B2

    公开(公告)日：2015-08-11

    申请号：US13722931

    申请日：2012-12-20

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Dipankar Pramanik

    IPC: H01L21/3065 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/28 ,  H01L21/768

    CPC classification number: H01L29/78 ,  H01L21/28255 ,  H01L21/3105 ,  H01L21/76823 ,  H01L21/76826

    Abstract: Conducting materials having narrow impurity conduction bands can reduce the number of high energy excitations, and can be prepared by a sequence of plasma treatments. For example, a dielectric layer can be exposed to a first plasma ambient to form vacancy sites, and the vacancy-formed dielectric layer can be subsequently exposed to a second plasma ambient to fill the vacancy sites with substitutional impurities.

    Abstract translation: 具有窄杂质导带的导电材料可以减少高能量激发的数量，并且可以通过一系列等离子体处理来制备。 例如，电介质层可以暴露于第一等离子体环境以形成空位，并且随后将空位形成的电介质层暴露于第二等离子体环境以用替代杂质填充空位。

    MoOx-based resistance switching materials
    15.
    发明授权
    MoOx-based resistance switching materials 有权
    基于MoOx的电阻开关材料

    公开(公告)号：US08907314B2

    公开(公告)日：2014-12-09

    申请号：US13727958

    申请日：2012-12-27

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Tony P. Chiang ,  Dipankar Pramanik

    IPC: H01L29/02 ,  H01L45/00

    CPC classification number: H01L45/145 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1641

    Abstract: Molybdenum oxide can be used to form switching elements in a resistive memory device. The atomic ratio of oxygen to molybdenum can be between 2 and 3. The molybdenum oxide exists in various Magneli phases, such as Mo13O33, Mo4O11, Mo17O47, Mo8O23, or Mo9O26. An electric field can be established across the switching layers, for example, by applying a set or reset voltage. The electric field can cause movement of the oxygen charges, e.g., O2− ions, changing the composition profile of the switching layers, forming bistable states, including a high resistance state with MoO3 and a low resistance state with MoOx (x

    Abstract translation: 氧化钼可用于在电阻式存储器件中形成开关元件。 氧与钼的原子比可以在2和3之间。氧化钼存在于各种Magneli相中，例如Mo13O33，Mo4O11，Mo17O47，Mo8O23或Mo9O26。 可以跨开关层建立电场，例如通过施加置位或复位电压。 电场可导致氧电荷的移动，例如O 2离子，改变开关层的组成分布，形成双稳态，包括具有MoO 3的高电阻状态和具有MoO x（x <3）的低电阻状态）。

    MoOx-Based Resistance Switching Materials
    16.
    发明申请
    MoOx-Based Resistance Switching Materials 有权
    基于MoOx的电阻开关材料

    公开(公告)号：US20140183432A1

    公开(公告)日：2014-07-03

    申请号：US13727958

    申请日：2012-12-27

    Applicant: INTERMOLECULAR, INC.

    Inventor： Sergey Barabash ,  Tony P. Chiang ,  Dipankar Pramanik

    IPC: H01L45/00

    CPC classification number: H01L45/145 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1641

    Abstract: Molybdenum oxide can be used to form switching elements in a resistive memory device. The atomic ratio of oxygen to molybdenum can be between 2 and 3. The molybdenum oxide exists in various Magneli phases, such as Mo13O33, Mo4O11, Mo17O47, Mo8O23, or Mo9O26. An electric field can be established across the switching layers, for example, by applying a set or reset voltage. The electric field can cause movement of the oxygen charges, e.g., O2− ions, changing the composition profile of the switching layers, forming bistable states, including a high resistance state with MoO3 and a low resistance state with MoOx (x

    Abstract translation: 氧化钼可用于在电阻式存储器件中形成开关元件。 氧与钼的原子比可以在2和3之间。氧化钼存在于各种Magneli相中，例如Mo13O33，Mo4O11，Mo17O47，Mo8O23或Mo9O26。 可以跨开关层建立电场，例如通过施加置位或复位电压。 电场可导致氧电荷的移动，例如O 2离子，改变开关层的组成分布，形成双稳态，包括具有MoO 3的高电阻状态和具有MoO x（x <3）的低电阻状态）。

    Controlling ReRam Forming Voltage with Doping
    18.
    发明申请
    Controlling ReRam Forming Voltage with Doping 有权
    用掺杂控制ReRam成型电压

    公开(公告)号：US20140166958A1

    公开(公告)日：2014-06-19

    申请号：US13719051

    申请日：2012-12-18

    Applicant: INTERMOLECULAR, INC.

    Inventor： Sergey Barabash ,  Charlene Chen ,  Dipankar Pramanik

    IPC: H01L45/00

    CPC classification number: H01L45/1616 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

    Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

    Abstract translation: 可以形成电阻式存储元件中的内部电场以降低成形电压。 可以通过在电阻式存储元件的开关电介质层内并入一个或多个带电层来形成内部电场。 带电层可以包括相邻的电荷层以形成偶极层。 带电层可以在开关电介质层的界面处或附近形成电极层。 此外，带电层可以朝向较低功函电极的较低价取代面取向，而朝较高功函电极取向较高的取代价。

    Electrode for low-leakage devices
    19.
    发明授权
    Electrode for low-leakage devices 有权
    低漏电极用电极

    公开(公告)号：US09245941B2

    公开(公告)日：2016-01-26

    申请号：US14140807

    申请日：2013-12-26

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Mankoo Lee ,  Dipankar Pramanik

    IPC: H01L21/28 ,  H01L49/02 ,  H01L21/02 ,  H01L27/108

    CPC classification number: H01L28/60 ,  H01L21/02156 ,  H01L21/02186 ,  H01L21/02356 ,  H01L21/28088 ,  H01L21/28229 ,  H01L27/1085 ,  H01L2924/0134 ,  H01L2924/0533 ,  H01L2924/05341 ,  H01L2924/10671

    Abstract: A YBCO-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. Alternatively, a material with a narrow conduction band can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the YBCO-based electrode or with the band gap of the narrow-band conductive material electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps of the YBCO-based or narrow-band conductive material, thermionic leakage through the dielectric can be reduced, since the excited electrons or holes in the electrode would need higher thermal excitation energy to overcome the band gap before passing through the dielectric layer.

    Abstract translation: 可以使用YBCO基导电材料作为电极，其可以与诸如高k电介质的电介质接触。 或者，具有窄导带的材料可以用作可以与诸如高k电介质的电介质接触的电极。 通过将电介质与YBCO基电极的带隙或窄带导电材料电极的带隙对准，例如，电介质的导带最小值落入基于YBCO的电极的带隙之一或 窄带导电材料可以减少通过电介质的热离子泄漏，因为电极中激发的电子或空穴需要较高的热激发能量以克服通过电介质层之前的带隙。

    Switching conditions for resistive random access memory cells
    20.
    发明授权
    Switching conditions for resistive random access memory cells 有权
    电阻随机存取存储单元的开关条件

    公开(公告)号：US09240236B1

    公开(公告)日：2016-01-19

    申请号：US14577613

    申请日：2014-12-19

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Dipankar Pramanik

    IPC: G11C11/00 ,  G11C13/00 ,  G11C29/50 ,  G11C29/02

    CPC classification number: G11C29/02 ,  G11C13/0007 ,  G11C29/50 ,  G11C2013/0083 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1641

    Abstract: Provided are method for determining switching conditions for production memory cells based on dopant flux during set and reset operations. One group of test memory cells, which are representative of the production memory cells, is subjected to a prolonged application of a set voltage, while another group is subjected to a prolonged application of a reset voltage. Different durations may be used for different cells in each group. A dopant concentration profile of a test component in each cell is determined for both groups. One cell from each group may be identified such that the changes in the dopant concentration profiles in these two identified cells are complementary. The profile complementarity indicates that these two identified cells had a similar dopant flux during voltage applications. Durations of set and reset voltage applications for these two cells may be used to determine switching conditions for production memory cells.

    Abstract translation: 提供了在设置和复位操作期间基于掺杂剂通量确定生产存储器单元的切换条件的方法。 代表生产存储器单元的一组测试存储单元经受长时间施加的设定电压，而另一组经受长时间应用复位电压。 不同的持续时间可以用于每组中的不同细胞。 确定每个细胞中测试组分的掺杂浓度分布。 可以鉴定每个组中的一个细胞，使得这两个鉴定的细胞中的掺杂剂浓度分布的变化是互补的。 配置互补性表明这两个识别的电池在电压施加期间具有相似的掺杂剂通量。 这两个单元的设定和复位电压应用的持续时间可用于确定生产存储单元的切换条件。

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