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    Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate
    11.
    发明申请
    Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate 审中-公开
    在半导体基板上筛选多个样品的组合处理方法

    公开(公告)号：US20140090596A1

    公开(公告)日：2014-04-03

    申请号：US14096981

    申请日：2013-12-04

    Applicant: Intermolecular, Inc.

    Inventor： Gaurav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G. Malhotra ,  Prashant B. Phatak ,  Kurt H. Weiner

    IPC: G01R31/28

    CPC classification number: G01R31/2831 ,  G01R31/2834 ,  H01L22/34

    Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

    Abstract translation: 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

    Resistive Switching Memory Element Including Doped Silicon Electrode
    15.
    发明申请
    Resistive Switching Memory Element Including Doped Silicon Electrode 有权
    包括掺杂硅电极的电阻式开关存储元件

    公开(公告)号：US20130292632A1

    公开(公告)日：2013-11-07

    申请号：US13935388

    申请日：2013-07-03

    Applicant: Intermolecular, Inc.

    Inventor： Prashant B. Phatak ,  Tony P. Chiang ,  Michael Miller ,  Wen Wu

    IPC: H01L45/00

    CPC classification number: H01L45/1616 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

    Abstract: A resistive switching memory is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching using unipolar or bipolar switching voltages for switching from a low resistance state to a high resistance state and vice versa.

    Abstract translation: 描述了一种电阻式开关存储器，其包括包括具有第一功函数的掺杂硅的第一电极，具有与第一功函数不同的第二功函数的第二电极在0.1和1.0电子伏特（eV）之间的金属氧化物 在第一电极和第二电极之间，金属氧化物层使用单极或双极开关电压进行大量介导的开关，用于从低电阻状态切换到高电阻状态，反之亦然。

    Titanium-Based High-K Dielectric Films
    16.
    发明申请
    Titanium-Based High-K Dielectric Films 有权
    钛基高K介电薄膜

    公开(公告)号：US20130044404A1

    公开(公告)日：2013-02-21

    申请号：US13657782

    申请日：2012-10-22

    Applicant: Intermolecular, Inc.

    Inventor： Hanhong Chen ,  Nobumichi Fuchigami ,  Imran Hashim ,  Edward L. Haywood ,  Pragati KUMAR ,  Sandra G. Malhotra ,  Monica Sawkar Mathur ,  Prashant B. Phatak ,  Sunil Shanker

    IPC: H01G4/30 ,  H01G4/018

    CPC classification number: H01G4/1218 ,  C23C16/405 ,  C23C16/45531 ,  C23C16/56 ,  H01G4/33 ,  H01L21/02186 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02312 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/3142 ,  H01L28/40

    Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle. The process provides high deposition rates, and the resulting MIM structure has substantially no x-ray diffraction peaks associated with anatase-phase titanium oxide.

    Abstract translation: 本公开内容提供（a）制造基于氧化钛的氧化物层（例如电介质层）的方法，以抑制锐钛矿相氧化钛的形成和（b）相关的器件和结构。 使用底部电极（或其他基底）的臭氧预处理随后进行ALD工艺形成金属 - 绝缘体 - 金属（MIM）堆叠，以形成使用含酰胺前体的TiO 2电介质。 在ALD工艺之后，氧化退火工艺的应用热度足以愈合TiO2电介质中的缺陷，并降低TiO2和电极之间的界面态; 选择退火温度以使其不那么热，以致破坏BEL表面粗糙度。 进一步的工艺变型可以包括在ALD工艺期间掺杂氧化钛，基座加热至275-300摄氏度，对于BEL使用铂或钌，对于每个ALD工艺循环使用多个试剂脉冲的臭氧。 该方法提供高沉积速率，并且所得MIM结构基本上没有与锐钛矿相氧化钛相关的x射线衍射峰。

    Doped Electrode for DRAM Capacitor Stack
    18.
    发明申请
    Doped Electrode for DRAM Capacitor Stack 有权
    用于DRAM电容堆栈的掺杂电极

    公开(公告)号：US20160099303A1

    公开(公告)日：2016-04-07

    申请号：US14507418

    申请日：2014-10-06

    Applicant: Intermolecular, Inc.

    Inventor： Prashant B. Phatak

    IPC: H01L49/02 ,  H01L27/108

    CPC classification number: H01L28/75 ,  H01L21/02197 ,  H01L21/2855 ,  H01L27/108 ,  H01L27/10805 ,  H01L28/65

    Abstract: In some embodiments, a metal oxide second electrode material is formed as part of a MIM DRAM capacitor stack. The second electrode material is doped with one or more dopants. The dopants may influence the crystallinity, resistivity, and/or work function of the second electrode material. The dopants may be uniformly distributed throughout the second electrode material or may be distributed with a gradient in their concentration profile.

    Abstract translation: 在一些实施例中，金属氧化物第二电极材料形成为MIM DRAM电容器堆叠的一部分。 第二电极材料掺杂有一种或多种掺杂剂。 掺杂剂可影响第二电极材料的结晶度，电阻率和/或功函数。 掺杂剂可以均匀分布在整个第二电极材料中，或者可以以它们的浓度分布梯度分布。

    TiOx Based Selector Element
    19.
    发明申请
    TiOx Based Selector Element 有权
    基于TiOx的选择元件

    公开(公告)号：US20150179933A1

    公开(公告)日：2015-06-25

    申请号：US14136365

    申请日：2013-12-20

    Applicant: Intermolecular, Inc.

    Inventor： Monica Sawkar Mathur ,  Venkat Ananthan ,  Mark Clark ,  Prashant B. Phatak

    IPC: H01L45/00

    CPC classification number: H01L27/2418 ,  H01L27/2463 ,  H01L45/00 ,  H01L45/08

    Abstract: Control elements that can be suitable for nonvolatile memory device applications are disclosed. The control element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The control element can be based on a single dielectric layer or on a multilayer dielectric stack.

    Abstract translation: 公开了可适用于非易失性存储器件应用的控制元件。 控制元件可以在低电压下具有低漏电流，以减少非选定器件的潜行电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件切换期间的电压降。 控制元件可以基于单个电介质层或多层电介质叠层。

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