公开(公告)号：US20180254361A1

公开(公告)日：2018-09-06

申请号：US15966864

申请日：2018-04-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： TZE-CHIANG CHEN ,  BAHMAN HEKMATSHOARTABARI ,  DEVENDRA K. SADANA ,  DAVOOD SHAHRJERDI

IPC: H01L31/0224 ,  H01L31/056 ,  H01L31/18 ,  H01L31/068 ,  H01L31/0376 ,  H01L31/0368 ,  H01L31/028 ,  H01L31/0747

CPC classification number: H01L31/0747 ,  H01L31/022458 ,  H01L31/056 ,  H01L31/068 ,  H01L31/1804 ,  Y02E10/50 ,  Y02E10/52 ,  Y02E10/546 ,  Y02E10/547 ,  Y02P70/521

Abstract: A photovoltaic device and method include a crystalline substrate and an emitter contact portion formed in contact with the substrate. A back-surface-field junction includes a homogeneous junction layer formed in contact with the crystalline substrate and having a same conductivity type and a higher active doping density than that of the substrate. The homogeneous junction layer includes a thickness less than a diffusion length of minority carriers in the homogeneous junction layer. A passivation layer is formed in contact with the homogeneous junction layer opposite the substrate, which is either undoped or has the same conductivity type as that of the substrate.

公开(公告)号：US20170059513A1

公开(公告)日：2017-03-02

申请号：US14841640

申请日：2015-08-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： ALI AFZALI-ARDAKANI ,  BAHMAN HEKMATSHOARTABARI ,  GHAVAM SHAHIDI

IPC: G01N27/414

CPC classification number: G01N27/4145

Abstract: Ion-sensitive field-effect transistors including channel regions of inorganic semiconductor material and organic gate junctions are provided for detecting biological materials or reactions within an electrolyte. The transistors may include self-assembled monolayers to passivate a surface of the inorganic semiconductor material. Bio-sensing material is immobilized by the self-assembled monolayers for use in bio-detection. A back-gate electrode is optionally employed.

Abstract translation: 包括无机半导体材料和有机栅极结的沟道区的离子敏感场效应晶体管用于检测电解质中的生物材料或反应。 晶体管可以包括自组装单层以钝化无机半导体材料的表面。 生物传感材料被自组装的单层固定，用于生物检测。 可以采用背栅电极。

公开(公告)号：US20160359068A1

公开(公告)日：2016-12-08

申请号：US15235216

申请日：2016-08-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： STEPHEN W. BEDELL ,  BAHMAN HEKMATSHOARTABARI ,  DEVENDRA K. SADANA ,  GHAVAM G. SHAHIDI ,  DAVOOD SHAHRJERDI

IPC: H01L31/0465 ,  H01L31/077 ,  H01L31/076 ,  H01L31/18 ,  H01L31/075 ,  H01L31/0224

CPC classification number: H01L31/0465 ,  H01L31/022466 ,  H01L31/046 ,  H01L31/0463 ,  H01L31/0475 ,  H01L31/0504 ,  H01L31/0684 ,  H01L31/0747 ,  H01L31/075 ,  H01L31/076 ,  H01L31/077 ,  H01L31/1876 ,  H01L31/1888 ,  H01L31/1896 ,  H01L31/204 ,  H01L31/208 ,  Y02E10/50

Abstract: A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.

公开(公告)号：US20160020344A1

公开(公告)日：2016-01-21

申请号：US14867553

申请日：2015-09-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： TZE-CHIANG CHEN ,  BAHMAN HEKMATSHOARTABARI ,  DEVENDRA K. SADANA ,  DAVOOD SHAHRJERDI

IPC: H01L31/0224 ,  H01L31/0368 ,  H01L31/0376 ,  H01L31/068 ,  H01L31/028

CPC classification number: H01L31/022458 ,  H01L31/028 ,  H01L31/03682 ,  H01L31/03762 ,  H01L31/056 ,  H01L31/068 ,  H01L31/0682 ,  H01L31/0684 ,  H01L31/0747 ,  H01L31/1804 ,  Y02E10/50 ,  Y02E10/52 ,  Y02E10/546 ,  Y02E10/547 ,  Y02P70/521

Abstract: A photovoltaic device and method include a crystalline substrate and an emitter contact portion formed in contact with the substrate. A back-surface-field junction includes a homogeneous junction layer formed in contact with the crystalline substrate and having a same conductivity type and a higher active doping density than that of the substrate. The homogeneous junction layer includes a thickness less than a diffusion length of minority carriers in the homogeneous junction layer. A passivation layer is formed in contact with the homogeneous junction layer opposite the substrate, which is either undoped or has the same conductivity type as that of the substrate.

Abstract translation: 光电器件和方法包括结晶衬底和形成为与衬底接触的发射极接触部分。 背表面场结包括与晶体衬底接触形成的均匀结层，并且具有与衬底相同的导电类型和更高的有源掺杂密度。 均匀结层包括小于均匀结层中的少数载流子的扩散长度的厚度。 形成与与衬底相对的均匀接合层接触的钝化层，其不掺杂或具有与衬底相同的导电类型。

公开(公告)号：US20150318425A1

公开(公告)日：2015-11-05

申请号：US14796546

申请日：2015-07-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： STEPHEN W. BEDELL ,  BAHMAN HEKMATSHOARTABARI ,  DEVENDRA K. SADANA ,  GHAVAM G. SHAHIDI ,  DAVOOD SHAHRJERDI

IPC: H01L31/0475 ,  H01L31/05

CPC classification number: H01L31/0465 ,  H01L31/022466 ,  H01L31/046 ,  H01L31/0463 ,  H01L31/0475 ,  H01L31/0504 ,  H01L31/0684 ,  H01L31/0747 ,  H01L31/075 ,  H01L31/076 ,  H01L31/077 ,  H01L31/1876 ,  H01L31/1888 ,  H01L31/1896 ,  H01L31/204 ,  H01L31/208 ,  Y02E10/50

Abstract: A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.

Abstract translation: 一种用于制造具有集成光伏电池的器件的方法包括在第一处理衬底上支撑半导体衬底并掺杂半导体衬底以形成具有相反导电性的掺杂交替区域。 掺杂层形成在半导体衬底的第一侧上。 在掺杂层上图案化导电材料以形成导电岛，使得导电岛与交替区对准以限定在单片结构上串联连接的多个光伏电池。

公开(公告)号：US20140227824A1

公开(公告)日：2014-08-14

申请号：US13966781

申请日：2013-08-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： TZE-CHIANG CHEN ,  BAHMAN HEKMATSHOARTABARI ,  DEVENDRA K. SADANA ,  DAVOOD SHAHRJERDI

IPC: H01L31/18 ,  H01L31/20

CPC classification number: H01L31/202 ,  H01L31/02167 ,  H01L31/022441 ,  H01L31/0747 ,  Y02E10/50

Abstract: A photovoltaic device includes a crystalline substrate having a first dopant conductivity, an interdigitated back contact and a front surface field structure. The front surface field structure includes a crystalline layer formed on the substrate and a noncrystalline layer formed on the crystalline layer. The crystalline layer and the noncrystalline layer are doped with dopants having an opposite dopant conductivity from that of the substrate. Methods are also disclosed.

公开(公告)号：US20140103485A1

公开(公告)日：2014-04-17

申请号：US13654040

申请日：2012-10-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： GREGORY M. FRITZ ,  BAHMAN HEKMATSHOARTABARI ,  ALI KHAKIFIROOZ ,  DIRK PFEIFFER ,  KENNETH P. RODBELL ,  DAVOOD SHAHRJERDI

IPC: H01L23/525

CPC classification number: H01L23/5252 ,  H01L23/576 ,  H01L27/24 ,  H01L27/2472 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to an antifuse for preventing a flow of electrical current in an integrated circuit. One such antifuse includes a reactive material and a silicon region thermally coupled to the reactive material, where an electrical current to the reactive material causes the reactive material to release heat which transitions the silicon region from a high resistance state to a low resistance state. Another such antifuse includes a reactive material, at least one metal and a silicon region adjacent to the at least one metal and thermally coupled to the reactive material, where an electrical current to the reactive material causes the reactive material to release heat which transitions the silicon region from a high resistance state to a low resistance state.

Abstract translation: 本公开涉及用于防止集成电路中的电流流动的反熔丝。 一种这样的反熔丝包括反应性材料和热耦合到反应性材料的硅区域，其中到反应性材料的电流导致反应性材料释放热量，其将硅区域从高电阻状态转变到低电阻状态。 另一种这样的反熔丝包括反应性材料，与至少一种金属相邻并且与反应性材料相邻的至少一个金属和硅区域，其中到反应性材料的电流导致反应性材料释放热量，其转移硅 区域从高电阻状态到低电阻状态。

公开(公告)号：US20170018606A1

公开(公告)日：2017-01-19

申请号：US15278816

申请日：2016-09-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KEVIN K. CHAN ,  BAHMAN HEKMATSHOARTABARI ,  TAK H. NING

IPC: H01L29/06 ,  H01L29/167 ,  H01L29/66 ,  H01L29/735

CPC classification number: H01L29/0638 ,  H01L27/06 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/167 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66234 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/735 ,  H01L29/7398

Abstract: A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region between the collector intrinsic region and the emitter intrinsic region. A collector extrinsic contact region is formed in direct contact with the collector intrinsic region; an emitter extrinsic contact region is formed on the emitter intrinsic region and a base extrinsic contact region is formed in direct contact with the intrinsic base region. Carbon is introduced into at least one of the collector extrinsic contact region, the emitter extrinsic contact region and the base extrinsic contact region to suppress diffusion of dopants into the junction region.

Abstract translation: 用于形成双极结型晶体管的方法包括在集电极本征区域和发射极本征区域之间形成集电极本征区域，发射极本征区域和本征基极区域。 集电体外部接触区域与集电极本征区域直接接触形成; 在发射极本征区域上形成发射极外部接触区域，并且形成与本征基极区域直接接触的基本非本征接触区域。 将碳引入到集电体外部本征接触区域，发射极非本征接触区域和基本非本征接触区域中的至少一个中，以抑制掺杂剂扩散到接合区域中。

公开(公告)号：US20160336424A1

公开(公告)日：2016-11-17

申请号：US15223988

申请日：2016-07-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： JOEL P. de SOUZA ,  BAHMAN HEKMATSHOARTABARI ,  JEEHWAN KIM ,  SIEGFRIED L. MAURER ,  DEVENDRA K. SADANA

IPC: H01L29/66 ,  H01L21/283 ,  H01L21/306

CPC classification number: H01L21/283 ,  A23C9/123 ,  A23C9/1315 ,  A23C11/08 ,  H01L21/2254 ,  H01L21/28114 ,  H01L21/30604 ,  H01L21/3213 ,  H01L21/32131 ,  H01L21/32133 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/66446 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78

Abstract: A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.

Abstract translation: 一种用于形成半导体器件的方法包括图案化形成在基底上的栅极导体和形成在栅极导体上的二维材料。 在衬底中形成与栅极导体相邻的凹陷，并且掺杂层沉积在凹部中并在二维材料的顶部上。 胶带粘附在二维材料顶部的掺杂层上。 去除带以从二维材料的顶部剥离掺杂层以在凹槽中形成源区和漏区。

公开(公告)号：US20160336418A1

公开(公告)日：2016-11-17

申请号：US15224035

申请日：2016-07-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： JOEL P. de SOUZA ,  BAHMAN HEKMATSHOARTABARI ,  JEEHWAN KIM ,  SIEGFRIED L. MAURER ,  DEVENDRA K. SADANA

IPC: H01L29/423 ,  H01L29/40

CPC classification number: H01L21/283 ,  A23C9/123 ,  A23C9/1315 ,  A23C11/08 ,  H01L21/2254 ,  H01L21/28114 ,  H01L21/30604 ,  H01L21/3213 ,  H01L21/32131 ,  H01L21/32133 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/66446 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78

Abstract: A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.