CHIP AUTHENTICATION USING SCAN CHAINS
    2.
    发明申请
    CHIP AUTHENTICATION USING SCAN CHAINS 有权
    使用扫描链的芯片认证

    公开(公告)号:US20150219718A1

    公开(公告)日:2015-08-06

    申请号:US14687561

    申请日:2015-04-15

    Abstract: Methods and systems for generating a circuit identification number include determining a propagation time delay across a scan chain of known length; comparing the propagation time delay to a threshold associated with the scan chain length; storing an identifier bit based on the result of the comparison; repeating the steps of determining, comparing, and storing until a number of stored identifier bits reaches a threshold number; and outputting the stored identifier bits.

    Abstract translation: 用于产生电路识别号码的方法和系统包括确定跨越已知长度的扫描链的传播时间延迟; 将传播时间延迟与扫描链长度相关联的阈值进行比较; 基于比较结果存储标识符位; 重复确定,比较和存储的步骤,直到多个存储的标识符比特达到阈值数; 并输出所存储的标识符位。

    PHYSICAL UNCLONABLE FUNCTION GENERATION AND MANAGEMENT
    3.
    发明申请
    PHYSICAL UNCLONABLE FUNCTION GENERATION AND MANAGEMENT 有权
    物理不可变函数生成与管理

    公开(公告)号:US20150236693A1

    公开(公告)日:2015-08-20

    申请号:US14699920

    申请日:2015-04-29

    CPC classification number: H03K19/003

    Abstract: Methods, systems and devices related to authentication of chips using physical unclonable functions (PUFs) are disclosed. In preferred systems, differentials of PUFs are employed to minimize sensitivity to temperature variations as well as other factors that affect the reliability of PUF states. In particular, a PUF system can include PUF elements arranged in series and in parallel with respect to each other to facilitate the measurement of the differentials and generation of a resulting bit sequence for purposes of authenticating the chip. Other embodiments are directed to determining and filtering reliable and unreliable states that can be employed to authenticate a chip.

    Abstract translation: 公开了使用物理不可克隆功能(PUF)的芯片认证相关的方法,系统和设备。 在优选的系统中,使用PUF的差异来最小化对温度变化的敏感性以及影响PUF状态的可靠性的其它因素。 特别地,PUF系统可以包括相对于彼此串联并联布置的PUF元件,以促进对差分的测量并产生所得到的位序列以便认证芯片。 其他实施例涉及确定和过滤可用于认证芯片的可靠和不可靠的状态。

    ANTIFUSE DEVICE FOR INTEGRATED CIRCUIT
    4.
    发明申请
    ANTIFUSE DEVICE FOR INTEGRATED CIRCUIT 有权
    用于集成电路的防装置

    公开(公告)号:US20140103485A1

    公开(公告)日:2014-04-17

    申请号:US13654040

    申请日:2012-10-17

    Abstract: The present disclosure relates to an antifuse for preventing a flow of electrical current in an integrated circuit. One such antifuse includes a reactive material and a silicon region thermally coupled to the reactive material, where an electrical current to the reactive material causes the reactive material to release heat which transitions the silicon region from a high resistance state to a low resistance state. Another such antifuse includes a reactive material, at least one metal and a silicon region adjacent to the at least one metal and thermally coupled to the reactive material, where an electrical current to the reactive material causes the reactive material to release heat which transitions the silicon region from a high resistance state to a low resistance state.

    Abstract translation: 本公开涉及用于防止集成电路中的电流流动的反熔丝。 一种这样的反熔丝包括反应性材料和热耦合到反应性材料的硅区域,其中到反应性材料的电流导致反应性材料释放热量,其将硅区域从高电阻状态转变到低电阻状态。 另一种这样的反熔丝包括反应性材料,与至少一种金属相邻并且与反应性材料相邻的至少一个金属和硅区域,其中到反应性材料的电流导致反应性材料释放热量,其转移硅 区域从高电阻状态到低电阻状态。

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