CONTACT FOR SILICON HETEROJUNCTION SOLAR CELLS
    2.
    发明申请
    CONTACT FOR SILICON HETEROJUNCTION SOLAR CELLS 有权
    联系太阳能电池太阳能电池

    公开(公告)号:US20150270424A1

    公开(公告)日:2015-09-24

    申请号:US14730502

    申请日:2015-06-04

    Abstract: A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion.

    Abstract translation: 光电器件和方法包括耦合到衬底的第一侧上的发射极侧结构的衬底和与衬底的第一侧相对的一侧的背侧结构。 发射极侧结构或背面结构包括在宽带隙层和窄带隙层之间交替的层,以提供与衬底有效增加的带偏移和/或在单个材料接触上有效地更高的掺杂水平的多层接触。 发射极触点耦合到器件的光收集端部上的发射极侧结构。 背面接触件与与光收集端部相对的背面结构耦合。

    CRYSTALLINE THIN-FILM TRANSISTOR
    7.
    发明申请
    CRYSTALLINE THIN-FILM TRANSISTOR 审中-公开
    晶体薄膜晶体管

    公开(公告)号:US20140191237A1

    公开(公告)日:2014-07-10

    申请号:US13967128

    申请日:2013-08-14

    Abstract: A method for forming a thin film transistor includes joining a crystalline substrate to an insulating substrate. A doped layer is deposited on the crystalline substrate, and the doped layer is patterned to form source and drain regions. The crystalline substrate is patterned to form an active area such that a conductive channel is formed in the crystalline substrate between the source and drain regions. A gate stack is formed between the source and drain regions, and contacts are formed to the source and drain regions and the gate stack through a passivation layer.

    Abstract translation: 一种形成薄膜晶体管的方法,包括将晶体衬底接合到绝缘衬底上。 掺杂层沉积在晶体衬底上,并且掺杂层被图案化以形成源区和漏区。 将晶体衬底图案化以形成有源区,使得在源区和漏区之间的晶体衬底中形成导电沟道。 在源极和漏极区域之间形成栅极堆叠,并且通过钝化层将触点形成到源极和漏极区域以及栅极堆叠。

Patent Agency Ranking