公开(公告)号：US10784156B2

公开(公告)日：2020-09-22

申请号：US15827613

申请日：2017-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Bartlet H. Deprospo ,  Huai Huang ,  Christopher J. Penny ,  Michael Rizzolo

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A conductive line structure comprises a first conductive line arranged in a first dielectric layer, a second conductive line arranged in the first dielectric layer, a cap layer arranged on the first conductive line and the second conductive line, and an airgap arranged between the first conductive line and the second conductive line, the airgap defined by the first dielectric layer and the cap layer.

公开(公告)号：US10763160B1

公开(公告)日：2020-09-01

申请号：US16362034

申请日：2019-03-22

Applicant: International Business Machines Corporation

Inventor： Christopher J. Penny ,  Benjamin D. Briggs ,  Michael Rizzolo ,  Lawrence A. Clevenger ,  Huai Huang ,  Hosadurga Shobha

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311

Abstract: Techniques are provided to fabricate semiconductor devices. For example, a semiconductor device can include an alternating arrangement of vertical metallic lines defining openings therebetween on a substrate. An interlevel dielectric layer is disposed on a consecutive first opening and a second opening to seal an air gap between a top surface of the substrate and a bottom surface of the interlevel dielectric layer.

公开(公告)号：US20200136028A1

公开(公告)日：2020-04-30

申请号：US16596152

申请日：2019-10-08

Applicant: International Business Machines Corporation

Inventor： Nicholas A. Lanzillo ,  Benjamin D. Briggs ,  Chih-Chao Yang ,  Hsueh-Chung Chen ,  Lawrence A. Clevenger

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A semiconductor structure includes a memory element disposed on a first metal layer. A first cap layer is disposed on the first metal layer and sidewalls of the memory element. A first dielectric layer is disposed on a top surface of the first cap layer on the first metal layer and a portion of the first cap layer on the sidewalls of the memory element. A second metal layer is disposed on the first dielectric layer and sidewalls of the first cap layer. A second cap layer is disposed on a top surface of the second metal layer. A second dielectric layer is disposed on the second cap layer. A via is in the second dielectric layer and exposes a top surface of the memory element. A third metal layer is disposed on the second dielectric layer and in the via.

公开(公告)号：US20200098499A1

公开(公告)日：2020-03-26

申请号：US16141195

申请日：2018-09-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas A. Lanzillo ,  Benjamin D. Briggs ,  Michael Rizzolo ,  Theodorus E. Standaert ,  Lawrence A. Clevenger ,  James Stathis

IPC: H01F10/32 ,  H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01F41/34

Abstract: An electrical device structure including a magnetic tunnel junction structure having a first tunnel junction dielectric layer positioned between a free magnetization layer and a fixed magnetization layer. A magnetization enhancement stack present on the magnetic tunnel junction structure. The magnetization enhancement stack includes a second tunnel junction layer that is in contact with the free magnetization layer of the magnetic tunnel junction structure, a metal contact layer present on the second tunnel junction layer, and a metal electrode layer present on the metal contact layer. A metallic ring on a sidewall of the magnetic enhancement stack, wherein a base of the metallic ring may be in contact with the free magnetization layer of the magnetic tunnel junction structure.

公开(公告)号：US20200065762A1

公开(公告)日：2020-02-27

申请号：US16111803

申请日：2018-08-24

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Leigh Anne H. Clevenger ,  Aldis Sipolins ,  Michael Rizzolo ,  Lawrence A. Clevenger ,  Christopher J. Penny

IPC: G06Q10/08 ,  B64C39/02 ,  G08G5/00 ,  G07C5/08

Abstract: Aspects include a system, method and computer program product for delivering a package via an unmanned aerial vehicle (UAV). A delivery parameter for delivering the package via the UAV is obtained. A weather parameter related to the delivery parameter is obtained. A flight configured for the UAV is selected, wherein the selected flight configuration reduces a delivery cost of the package via the UAV based on the weather parameter and the delivery parameter. The package is delivered using the selected flight configuration of the UAV.

公开(公告)号：US20190355668A1

公开(公告)日：2019-11-21

申请号：US15983689

申请日：2018-05-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael Rizzolo ,  Chih-Chao Yang ,  Lawrence A. Clevenger ,  Benjamin D. Briggs

IPC: H01L23/544 ,  H01L27/22

Abstract: A semiconductor device and method for forming the semiconductor device are described. The method includes recessing a device pad to below a top surface of an interconnect layer and depositing a cap in the recess over the device pad. A topography assist layer is formed over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap. Device layers are deposited conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer. The device pad is aligned according to the topographical feature.

公开(公告)号：US20190318960A1

公开(公告)日：2019-10-17

申请号：US16451269

申请日：2019-06-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Terry A. Spooner ,  Theodorus E. Standaert

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311 ,  H01L21/3105

Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.

公开(公告)号：US20190313533A1

公开(公告)日：2019-10-10

申请号：US15949741

申请日：2018-04-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Spyridon Skordas ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Benjamin D. Briggs ,  Michael Rizzolo ,  Maryam Ashoori ,  Arvind Kumar

IPC: H05K3/28 ,  H01L25/00 ,  H01L33/52 ,  H01L25/16 ,  H01L21/56 ,  H05K3/30

Abstract: Methods for orientation and placement of computing devices are presented. Aspects include applying, using a viscous material application device, a layer of a viscous material to a surface of an object, the layer of the viscous material having a plurality of computing devices disposed therein. The layer of the viscous material is allowed to dry during a drying period, wherein each of the plurality of computing devices comprises a first material applied to a first side of each of the plurality of computing devices, the first material having a first characteristic. And each of the plurality of computing devices comprises a second material applied to a second side of each of the plurality of computing devices, the second material having a second characteristic. And each of the plurality of computing devices is configured to perform, during the drying period, a self-orientation operation.

公开(公告)号：US20190304733A1

公开(公告)日：2019-10-03

申请号：US16427918

申请日：2019-05-31

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo

IPC: H01J21/10 ,  G06F17/50 ,  H01J19/24 ,  H01J9/02

Abstract: A field emission transistor includes a gate, a fold over emitter, and fold over collector. The emitter and the collector are separated from the gate by a void and are separated from a gate contact by gate contact dielectric. The void may be a vacuum, ambient air, or a gas. Respective ends of the emitter and the collector are separated by a gap. Electrons are drawn across gap from the emitter to the collector by an electrostatic field created when a voltage is applied to the gate. The emitter and collector include a first conductive portion substantially parallel with gate and a second conductive portion substantially perpendicular with gate. The second conductive portion may be formed by bending a segment of the first conductive portion. The second conductive portion is folded inward from the first conductive portion towards the gate. Respective second conductive portions are generally aligned.

公开(公告)号：US20190214558A1

公开(公告)日：2019-07-11

申请号：US15867044

申请日：2018-01-10

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Lawrence A. Clevenger ,  Chih-Chao Yang ,  Benjamin D. Briggs

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L45/1273 ,  G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/52 ,  H01L27/2463 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1675

Abstract: Methods and devices are provided for fabricating a resistive random-access array having dedicated electroforming contacts. A lower conductive line is formed on an interlayer dielectric layer. A lower electrode is formed on the lower conductive line. An isolation layer is formed having an upper surface which is coplanar with an upper surface of the lower electrode. A stack structure including a metal-oxide layer and upper electrode is formed on the lower electrode. Insulating spacers are formed on sidewalls of the stack structure. The lower electrode, and stack structure form a resistive memory cell, wherein a footprint of the lower electrode is greater than that of the upper electrode. An upper conductive line contacts the upper electrode, and is arranged orthogonal to the lower conductive line. A dedicated electroforming contact contacts an extended portion of the lower electrode which extends past a cross-point of the upper and lower conductive lines.