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    III-V, SiGe, or Ge Base Lateral Bipolar Transistor and CMOS Hybrid Technology
    18.
    发明申请
    III-V, SiGe, or Ge Base Lateral Bipolar Transistor and CMOS Hybrid Technology 有权
    III-V，SiGe或Ge基侧向双极晶体管和CMOS混合技术

    公开(公告)号：US20150287642A1

    公开(公告)日：2015-10-08

    申请号：US14245627

    申请日：2014-04-04

    Applicant: International Business Machines Corporation

    Inventor： Josephine B. Chang ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

    IPC: H01L21/8249 ,  H01L21/02 ,  H01L21/24 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/735 ,  H01L29/66 ,  H01L21/285

    CPC classification number: H01L21/8249 ,  H01L21/244 ,  H01L21/84 ,  H01L27/0623 ,  H01L29/1008 ,  H01L29/456 ,  H01L29/6625 ,  H01L29/66545 ,  H01L29/735

    Abstract: In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.

    Abstract translation: 一方面，在晶片上制造双极晶体管器件的方法包括以下步骤。 在晶片上形成虚拟栅极，其中伪栅极存在于作为双极晶体管的基极的晶片的一部分上。 晶圆被掺杂以在虚拟栅极的两侧上形成发射极和集电极区域。 介电填料层沉积在围绕虚拟栅极的晶片上。 对绝缘填料层选择性地去除伪栅极，从而露出基底。 基座凹进。 碱从由SiGe，Ge和III-V材料组成的组中选择的外延材料再生长。 触点形成在基座上。 还提供了用于共同制造双极晶体管和CMOS FET器件的技术。

    High-rate chemical vapor etch of silicon substrates
    19.
    发明授权
    High-rate chemical vapor etch of silicon substrates 有权
    硅衬底的高速化学气相蚀刻

    公开(公告)号：US08927431B2

    公开(公告)日：2015-01-06

    申请号：US13906392

    申请日：2013-05-31

    Applicant: International Business Machines Corporation

    Inventor： Stephen W. Bedell ,  Gen P. Lauer ,  Isaac Lauer ,  Joseph S. Newbury

    IPC: H01L21/311 ,  H01L21/306 ,  H01L21/308

    CPC classification number: H01L21/3065

    Abstract: Methods of etching a silicon substrate at a high rate using a chemical vapor etching process are provided. A silicon substrate may be etched by heating the silicon substrate in a process chamber and then flowing hydrochloric acid and a germanium-carrying compound into the process chamber. The substrate may be heated to at least 700° C. The hydrochloric acid flow rate may be at least approximately 100 (standard cubic centimeters per minute) sccm. In some embodiments, the hydrochloric acid flow rate may be between approximately 10 slm and approximately 20 standard liters per minute (slm). The germanium-carrying compound flow rate may be at least approximately 50 sccm. In some embodiments, the germanium-carrying compound flow rate may be between approximately 100 sccm and approximately 500 sccm. The etching may extend fully through the silicon substrate.

    Abstract translation: 提供了使用化学气相蚀刻工艺以高速度蚀刻硅衬底的方法。 可以通过在处理室中加热硅衬底然后将盐酸和含锗化合物流入处理室来蚀刻硅衬底。 衬底可以被加热到至少700℃。盐酸流速可以是至少约100（标准立方厘米每分钟）sccm。 在一些实施方案中，盐酸流速可以在约10slm至约20标准升/分钟（slm）之间。 携带锗的化合物流速可以至少为约50sccm。 在一些实施方案中，携带锗的化合物流速可以在约100sccm至约500sccm之间。 蚀刻可以完全延伸穿过硅衬底。

    Structure and method to reduce shorting and process degradation in stt-MRAM devices
    20.
    发明授权
    Structure and method to reduce shorting and process degradation in stt-MRAM devices 有权

    公开(公告)号：US10256397B2

    公开(公告)日：2019-04-09

    申请号：US15906480

    申请日：2018-02-27

    Applicant: International Business Machines Corporation

    Inventor： Anthony J. Annunziata ,  Gen P. Lauer ,  Janusz J. Nowak ,  Eugene J. O'Sullivan

    IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12

    Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.

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