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1.发明授权公开(公告)号：US09698339B1
公开(公告)日：2017-07-04
申请号：US14982540
申请日：2015-12-29
发明人： Anthony J. Annunziata , Marinus Hopstaken , Chandrasekara Kothandaraman , JungHyuk Lee , Deborah A. Neumayer , Jeong-Heon Park
摘要： Embodiments are directed to an electromagnetic memory device having a memory cell and an encapsulation layer formed over the memory cell. The memory cell may include a magnetic tunnel junction (MTJ), and the encapsulation layer may be formed from a layer of hydrogenated amorphous silicon. Amorphous silicon improves the coercivity of the MTJ but by itself is conductive. Adding hydrogen to amorphous silicon passivates dangling bonds of the amorphous silicon, thereby reducing the ability of the resulting hydrogenated amorphous silicon layer to provide a parasitic current path to the MTJ. The hydrogenated amorphous silicon layer may be formed using a plasma-enhanced chemical vapor deposition, which can be tuned to enable a hydrogen level of approximately 10 to approximately 20 percent. By keeping subsequent processing operations at or below about 400 Celsius, the resulting layer of hydrogenated amorphous silicon can maintain its hydrogen level of approximately 10 to 20 percent.
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2.发明授权Low degradation MRAM encapsulation process using silicon-rich silicon nitride film 有权使用富硅氮化硅薄膜的低降解MRAM封装工艺公开(公告)号：US09515252B1
公开(公告)日：2016-12-06
申请号：US14983015
申请日：2015-12-29
发明人： Anthony J. Annunziata , Chandrasekaran Kothandaraman , Gen P. Lauer , JungHyuk Lee , Nathan P. Marchack , Deborah A. Neumayer , Eugene J. O'Sullivan , Jeong-Heon Park
CPC分类号： H01L43/08 , G11C11/161 , G11C11/1677 , H01L27/22 , H01L27/222 , H01L43/02 , H01L43/12
摘要： A method of making a magnetic random access memory (MRAM) device comprising forming a magnetic tunnel junction on an electrode, the magnetic tunnel junction comprising a first reference layer, a free layer, and a first tunnel barrier layer; and depositing an encapsulating silicon nitride film on and along sidewalls of the magnetic tunnel junction; wherein the silicon nitride film has a N:Si ratio from 0.1 to 1. An MRAM device made by the above method is also disclosed.
摘要翻译： 一种制造磁性随机存取存储器（MRAM）装置的方法，包括在电极上形成磁性隧道结，所述磁性隧道结包括第一参考层，自由层和第一隧道势垒层; 以及在所述磁性隧道结的侧壁上并沿着所述磁性隧道结的侧壁沉积封装的氮化硅膜; 其中氮化硅膜具有0.1:1的N:Si比率。还公开了通过上述方法制造的MRAM器件。
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3.发明申请公开(公告)号：US20170186943A1
公开(公告)日：2017-06-29
申请号：US14982540
申请日：2015-12-29
发明人： Anthony J. Annunziata , Marinus Hopstaken , Chandrasekara Kothandaraman , JungHyuk Lee , Deborah A. Neumayer , Jeong-Heon Park
摘要： Embodiments are directed to an electromagnetic memory device having a memory cell and an encapsulation layer formed over the memory cell. The memory cell may include a magnetic tunnel junction (MTJ), and the encapsulation layer may be formed from a layer of hydrogenated amorphous silicon. Amorphous silicon improves the coercivity of the MTJ but by itself is conductive. Adding hydrogen to amorphous silicon passivates dangling bonds of the amorphous silicon, thereby reducing the ability of the resulting hydrogenated amorphous silicon layer to provide a parasitic current path to the MTJ. The hydrogenated amorphous silicon layer may be formed using a plasma-enhanced chemical vapor deposition, which can be tuned to enable a hydrogen level of approximately 10 to approximately 20 percent. By keeping subsequent processing operations at or below about 400 Celsius, the resulting layer of hydrogenated amorphous silicon can maintain its hydrogen level of approximately 10 to 20 percent.
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公开(公告)号：US11220742B2
公开(公告)日：2022-01-11
申请号：US16362128
申请日：2019-03-22
发明人： Steven J. Holmes , Deborah A. Neumayer , Stephen Bedell , Devendra K. Sadana , Damon Farmer , Nathan P. Marchack
摘要： A method of fabricating a glassy carbon film is described. The method includes forming a soluble layer on a substrate, forming a lift-off stack that includes a lift-off mask layer and a hard-mask layer, and forming a pattern in the lift-off stack to expose a portion of the soluble layer. The exposed portions of the soluble layer are removed to expose a portion of the substrate. A carbon material is over the exposed portion of the substrate. The soluble layer is dissolved in a solvent, and the lift-off stack is lifted-off.
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公开(公告)号：US10727114B2
公开(公告)日：2020-07-28
申请号：US15405440
申请日：2017-01-13
发明人： Robert L. Bruce , Alfred Grill , Eric A. Joseph , Teddie P. Magbitang , Hiroyuki Miyazoe , Deborah A. Neumayer
IPC分类号： H01L23/52 , H01L21/768 , H01L23/532
摘要： Integrated circuits including at least two electrically conductive interconnect lines and methods of manufacturing generally include a surface of the integrated circuit. At least two electrically conductive interconnect lines are separated by a space of less than 90 nm and are formed on the surface. Each of the at least two interconnect lines includes a metal cap, a copper conductor having an average grain size greater than a line width of the interconnect. A liner layer is provided, wherein the liner layer and the metal cap encapsulate the copper conductor. A dielectric layer overlaying the at least two electrically conductive interconnect lines and extending along sidewalls thereof is provided, wherein the dielectric layer is configured to provide an airgap between the at least two interconnect lines at the spacing.
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6.发明申请NEUTRAL HARD MASK AND ITS APPLICATION TO GRAPHOEPITAXY-BASED DIRECTED SELF-ASSEMBLY (DSA) PATTERNING 有权中性硬帘及其应用于基于花岗质的指导自组装（DSA）图案公开(公告)号：US20170025274A1
公开(公告)日：2017-01-26
申请号：US14806921
申请日：2015-07-23
IPC分类号： H01L21/033 , H01L21/027
CPC分类号： H01L21/0337 , B81C1/00396 , G03F7/0002 , G03F7/094
摘要： A material stack is formed on the surface of a semiconductor substrate. The top layer of the material stack comprises at least an organic planarization layer. A neutral hard mask layer is formed on the top of the organic planarization layer. The neutral hard mask layer is neutral to the block copolymers used for direct self-assembly. A plurality of template etch stacks are then formed on top of the neutral hard mask layer. After formation of the template etch stacks, neutrality recovery is performed on the neutral hard mask layer and the top portions of the template etch stacks, the vertical sidewalls of the template etch stacks being substantially unaffected by the neutrality recovery. A template for DSA is thus obtained.
摘要翻译： 材料堆叠形成在半导体衬底的表面上。 材料堆叠的顶层至少包括有机平坦化层。 在有机平坦化层的顶部形成中性硬掩模层。 中性硬掩模层对于用于直接自组装的嵌段共聚物是中性的。 然后在中性硬掩模层的顶部上形成多个模板蚀刻堆叠。 在形成模板蚀刻堆叠之后，在中性硬掩模层和模板蚀刻堆叠的顶部进行中性恢复，模板蚀刻堆叠的垂直侧壁基本上不受中性恢复的影响。 因此获得DSA的模板。
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公开(公告)号：US20160329211A1
公开(公告)日：2016-11-10
申请号：US15211010
申请日：2016-07-15
发明人： Kevin K. Chan , Marinus J.P. Hopstaken , Young-Hee Kim , Masaharu Kobayashi , Effendi Leobandung , Deborah A. Neumayer , Dae-Gyu Park , Uzma Rana , Tsong-Lin Tai
IPC分类号： H01L21/24 , H01L29/66 , H01L21/225 , H01L29/267 , H01L21/322 , H01L21/324
CPC分类号： H01L21/242 , H01L21/2257 , H01L21/2258 , H01L21/28575 , H01L21/3228 , H01L21/3245 , H01L29/267 , H01L29/452 , H01L29/517 , H01L29/665 , H01L29/66522 , H01L29/66742 , H01L29/78618 , H01L29/78681
摘要： An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.
摘要翻译： 提供在半导体器件中形成掺杂剂结的方法的方法。 该方法包括对半导体层的暴露表面进行表面改性处理，并在半导体层的暴露表面上沉积掺杂剂材料。 此外，该方法包括使金属层与掺杂剂层合金以形成半导体器件结，其中半导体层由III-V族半导体材料组成，表面改性处理发生在真空室中以从暴露的表面去除表面氧化物 半导体层的表面，并且上述每个过程在低温下发生。
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8.发明申请BORON RICH NITRIDE CAP FOR TOTAL IONIZING DOSE MITIGATION IN SOI DEVICES 有权BORON RICH NITRIDE CAP FOR TOTAL IONIZING DOSE FATIGATION IN SOI DEVICES公开(公告)号：US20150243740A1
公开(公告)日：2015-08-27
申请号：US14187742
申请日：2014-02-24
CPC分类号： H01L29/0653 , H01L21/02488 , H01L21/7624 , H01L27/1203 , H01L29/0603 , H01L29/78603
摘要： A semiconductor-on-insulator (SOI) structure that includes a cap layer composed of a boron-rich compound or doped boron nitride located between a top semiconductor layer and a buried insulator layer is provided. The cap layer forms a conductive path between the top semiconductor layer and the buried insulator layer in the SOI structure to dissipate total ionizing dose (TID) accumulated charges, thus advantageously mitigating TID effects in fully depleted SOI transistors.
摘要翻译： 提供了一种绝缘体上半导体（SOI）结构，其包括由位于顶部半导体层和掩埋绝缘体层之间的富硼化合物或掺杂氮化硼构成的覆盖层。 盖层在SOI结构中在顶部半导体层和掩埋绝缘体层之间形成导电路径，以耗散总电离剂量（TID）的累积电荷，从而有利地减轻完全耗尽的SOI晶体管中的TID效应。
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9.发明授权Laser doping of crystalline semiconductors using a dopant-containing amorphous silicon stack for dopant source and passivation 有权使用含掺杂剂的非晶硅叠层对掺杂剂源和钝化的激光掺杂晶体半导体公开(公告)号：US09112068B2
公开(公告)日：2015-08-18
申请号：US13646120
申请日：2012-10-05
IPC分类号： H01L31/0224 , H01L31/068 , H01L31/0747 , H01L31/18
CPC分类号： H01L31/022425 , H01L21/02532 , H01L21/02592 , H01L21/02686 , H01L21/2257 , H01L21/268 , H01L21/76838 , H01L31/068 , H01L31/0747 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： Techniques and structures for laser doping of crystalline semiconductors using a dopant-containing amorphous silicon stack for dopant source and passivation. A structure includes a crystalline semiconductor having at least one surface, a doped crystalline region disposed in at least one selected area of the semiconductor surface, and a dopant-containing amorphous silicon layer stack containing a same dopant as present in the doped crystalline region on at least a portion of the semiconductor surface outside the selected area, wherein the dopant-containing amorphous silicon layer stack passivates the portion of the semiconductor surface on which it is disposed.
摘要翻译： 使用含掺杂剂的非晶硅叠层进行掺杂剂源和钝化的晶体半导体激光掺杂的技术和结构。 一种结构包括具有至少一个表面的晶体半导体，设置在半导体表面的至少一个选定区域中的掺杂晶体区域，以及含有掺杂剂的非晶硅层堆叠，其含有与存在于掺杂晶体区域 半导体表面的至少一部分在选定区域之外，其中含掺杂剂的非晶硅层叠层钝化其所在的半导体表面的部分。
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公开(公告)号：US20140127896A1
公开(公告)日：2014-05-08
申请号：US14148183
申请日：2014-01-06
发明人： Griselda Bonilla , Christos D. Dimitrakopoulos , Alfred Grill , James B. Hannon , Qinghuang Lin , Deborah A. Neumayer , Satoshi Oida , John A. Ott , Dirk Pfeiffer
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , H01L21/76835 , H01L21/76846 , H01L21/76849 , H01L21/76852 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.
摘要翻译： 提供了包括位于铜结构的暴露表面上的石墨烯盖的互连结构。 在一些实施例中，石墨烯盖仅位于铜结构的最上表面的顶部，而在其它实施例中，石墨烯盖位于垂直侧壁和铜结构的最上表面的顶部。 铜结构位于电介质材料内。
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