公开(公告)号：US20180061750A1

公开(公告)日：2018-03-01

申请号：US15251450

申请日：2016-08-30

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Jessica Dechene ,  Elbert Huang ,  Joe Lee

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4803 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/49872 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/5329 ,  H01L23/53295

Abstract: A multi-level semiconductor device and a method of fabricating a multi-level semiconductor device involve a first interlayer dielectric (ILD) layer with one or more metal lines formed therein. A silicide is formed on a surface of the first ILD layer and is directly adjacent to each of the one or more metal lines on both sides of each of the one or more metal lines. A second ILD is formed above the silicide, and a via is formed through the second ILD above one of the one or more metal lines. One or more second metal lines are formed above the second ILD, one of which is formed in the via. The second metal line in the via contacts the one of the one or more metal lines and the silicide adjacent to the one of the one or more metal lines.

公开(公告)号：US09252051B1

公开(公告)日：2016-02-02

申请号：US14540367

申请日：2014-11-13

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Joe Lee ,  Yann Mignot ,  Douglas M. Trickett

IPC: H01L21/302 ,  H01L21/768

CPC classification number: H01L21/76819 ,  H01L21/76804 ,  H01L21/76811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: After completely etching through a material stack comprising an oxide hard mask layer and an underlying interlevel dielectric (ILD) layer formed on a substrate to provide at least one opening, top corners of the at least one opening are rounded by performing a plasma etch employing a combination of an etching gas and a deposition gas comprising a hydrofluorocarbon compound. The hydrofluorocarbon compound forms a hydrofluorocarbon polymer layer on sidewalls of the at least one opening and helps to preserve the profile of the at least one opening.

Abstract translation: 在通过包括氧化物硬掩模层和形成在衬底上的下面的层间电介质（ILD）层的材料堆完全蚀刻以提供至少一个开口之后，通过执行等离子体蚀刻来使至少一个开口的顶角变圆， 蚀刻气体和包含氢氟烃化合物的沉积气体的组合。 氢氟烃化合物在至少一个开口的侧壁上形成氢氟烃聚合物层，有助于保持至少一个开口的轮廓。

公开(公告)号：US20240429103A1

公开(公告)日：2024-12-26

申请号：US18340969

申请日：2023-06-26

Applicant: International Business Machines Corporation

Inventor： Tao Li ,  Joe Lee ,  Ruilong Xie ,  Kisik Choi

IPC: H01L21/8234 ,  H01L21/768 ,  H01L23/528 ,  H01L27/088 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate including shallow trench isolation (STI) regions, a semiconductor fin between the STI regions, and a STI liner on an upper surface of the STI regions. A STI layer is in each of the STI regions, and includes a liner opening exposing a portion of the STI layer. A source/drain is on a sidewall of the semiconductor fin. A multi-stage backside contact is on the source/drain and contacting the portion of the STI layer via the liner opening.

公开(公告)号：US20240038535A1

公开(公告)日：2024-02-01

申请号：US17875756

申请日：2022-07-28

Applicant: International Business Machines Corporation

Inventor： Joe Lee ,  Yann Mignot ,  Christopher J. Penny ,  Koichi Motoyama

IPC: H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/0276 ,  H01L21/0335 ,  H01L21/0332

Abstract: A method of forming a mandrel for use in a pitch doubling process is provided in which a metal hard mask is inserted between a mandrel material layer and a soft mask. The insertion of the metal hard mask allows for easier pattern transfer into the mandrel material layer and avoids many issues encountered during multi-patterning steps. The insertion of the metal hard mask forms a square mandrel that has a flat top due to durability against etch and ability to wet strip the metal hard mask. The metal hard mask can be tuned before pattern transfer into the underlying mandrel material layer to provide a hard mask pattern that is smaller or larger than the pattern without performing such tuning. The method also can be used to protect the downstream non-mandrel processes where selectivity is crucial.

公开(公告)号：US11366671B2

公开(公告)日：2022-06-21

申请号：US16851377

申请日：2020-04-17

Applicant: International Business Machines Corporation

Inventor： Kenneth L. Ward ,  Susan E. Eisen ,  Dung Q. Nguyen ,  Glenn O. Kincaid ,  Joe Lee ,  Deepak K. Singh

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/34

Abstract: Method and apparatus for a completion mechanism for a microprocessor are provided by identifying entries in a section of an Instruction Completion Table (ICT) that are marked as ready to complete via corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion; determining a head pointer that indicates an end of the entries in the ICT that are ready for completion; completing instructions included in the entries between the tail pointer and the head pointer; and updating the tail pointer to a value of the head pointer for a subsequent instruction completion round.

公开(公告)号：US10276436B2

公开(公告)日：2019-04-30

申请号：US15229470

申请日：2016-08-05

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Jessica Dechene ,  Elbert E. Huang ,  Joe Lee ,  Theodorus E. Standaert

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

公开(公告)号：US20180315653A1

公开(公告)日：2018-11-01

申请号：US16014020

申请日：2018-06-21

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Jessica Dechene ,  Elbert E. Huang ,  Joe Lee ,  Theodorus E. Standaert

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/7681 ,  H01L21/76834 ,  H01L21/7684 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2221/1021

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

公开(公告)号：US20180240971A1

公开(公告)日：2018-08-23

申请号：US15805882

申请日：2017-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Joe Lee ,  Christopher J. Penny ,  Michael Rizzolo ,  Chih-Chao Yang

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving a metal, depositing one or more sacrificial layers, and etching portions of the one or more sacrificial layers to expose a top surface of the metal of one or more of the trenches. The method further includes selectively depositing an electrode over the top surface of the exposed metal and nitridizing the electrode to form a diffusion barrier between chip components and the metal.

公开(公告)号：US10020255B1

公开(公告)日：2018-07-10

申请号：US15798794

申请日：2017-10-31

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Joe Lee ,  Yann Mignot ,  Hosadurga Shobha ,  Junli Wang ,  Yongan Xu

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76879 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295

Abstract: Semiconductor devices including super via structures and BEOL processes for forming the same, according to embodiments of the invention, generally include removing selected portions of a nitride cap layer intermediate interconnect levels, wherein the selected portions correspond to the regions where the super via structure is to be formed and where underlying overlay alignment markers are located.

公开(公告)号：US20180122692A1

公开(公告)日：2018-05-03

申请号：US15852176

申请日：2017-12-22

Applicant: International Business Machines Corporation

Inventor： Benjamin David Briggs ,  Joe Lee ,  Theodorus Eduardus Standaert

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76831 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238

Abstract: A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.