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公开(公告)号:US10276626B2
公开(公告)日:2019-04-30
申请号:US15857086
申请日:2017-12-28
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Qing Cao , Shu-Jen Han
IPC: H01L27/146 , H01L31/032 , H01L31/0296
Abstract: A three-dimensional multispectral imaging sensor and method for forming a three-dimensional multispectral imaging sensor are provided. The three-dimensional multispectral imaging sensor includes a monolithic structure having a plurality of layers. Each of the layers is formed from light detecting materials for detecting light of respective different non-overlapping wavelengths and having respective different bandgaps.
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公开(公告)号:US10079149B2
公开(公告)日:2018-09-18
申请号:US15588976
申请日:2017-05-08
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Qing Cao , Shu-Jen Han , Ning Li , Jianshi Tang
CPC classification number: H01L21/2807 , B82Y10/00 , H01L21/26513 , H01L21/28088 , H01L21/32056 , H01L29/0673 , H01L29/0847 , H01L29/401 , H01L29/4966 , H01L29/517 , H01L29/6653 , H01L29/6656 , H01L29/66568 , H01L29/775 , H01L29/78
Abstract: A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.
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公开(公告)号:US10062857B2
公开(公告)日:2018-08-28
申请号:US15594233
申请日:2017-05-12
Applicant: International Business Machines Corporation
Inventor: Qing Cao , Kangguo Cheng , Zhengwen Li , Fei Liu
CPC classification number: H01L51/0562 , H01J21/105 , H01L29/0673 , H01L51/0017 , H01L51/0048 , H01L51/0504 , H01L51/0545 , H01L51/0558
Abstract: Vacuum transistors with carbon nanotube as the collector and/or emitter electrodes are provided. In one aspect, a method for forming a vacuum transistor includes the steps of: covering a substrate with an insulating layer; forming a back gate(s) in the insulating layer; depositing a gate dielectric over the back gate; forming a carbon nanotube layer on the gate dielectric; patterning the carbon nanotube layer to provide first/second portions thereof over first/second sides of the back gate, separated from one another by a gap G, which serve as emitter and collector electrodes; forming a vacuum channel in the gate dielectric; and forming metal contacts to the emitter and collector electrodes. Vacuum transistors are also provided.
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公开(公告)号:US20180205031A1
公开(公告)日:2018-07-19
申请号:US15407616
申请日:2017-01-17
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Qing Cao , Kangguo Cheng , Zhengwen Li , Fei Liu
CPC classification number: H01L51/5012 , B82Y20/00 , H01L27/3262 , H01L27/3276 , H01L51/5221 , H01L51/56
Abstract: A technique relates to a vertical device. A gate is embedded in a transparent substrate. A gate dielectric material is disposed on the gate. A nanotube film is disposed on the gate dielectric material. A quantum dot light emitting diode is disposed on a portion of the nanotube film.
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公开(公告)号:US20180200785A1
公开(公告)日:2018-07-19
申请号:US15407432
申请日:2017-01-17
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Qing Cao , Kangguo Cheng , Juntao Li
IPC: B22F1/00 , H01L21/02 , H01L21/225 , H01L21/321 , H01L21/027 , H01L21/3065 , H01L21/311 , H01L21/306 , C09K11/66 , B22F9/16 , B22F9/02
Abstract: A method for forming nanoparticles includes forming a stack of alternating layers including a first material disposed between a second material. The stack of alternating layers is patterned to form pillars. A dielectric layer is conformally deposited over the pillars. The pillars are annealed in an oxygen environment to modify a shape of the first material of the alternating layers. The dielectric layer and the second material are etched selectively to the first material to form nanoparticles from the first material.
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公开(公告)号:US20180145270A1
公开(公告)日:2018-05-24
申请号:US15863202
申请日:2018-01-05
Applicant: International Business Machines Corporation
Inventor: Qing Cao , Kangguo Cheng , Shu-Jen Han , Zhengwen Li , Fei Liu
CPC classification number: H01L51/0545 , H01L27/283 , H01L51/0006 , H01L51/0017 , H01L51/0021 , H01L51/0048 , H01L51/055 , H01L51/0558 , H01L51/105
Abstract: A method of arranging at least one carbon nanotube on a semiconductor substrate includes depositing the at least one carbon nanotube on a dielectric layer of the semiconductor device. The method further includes arranging the at least one carbon nanotube on the dielectric layer in response to applying a voltage potential to an electrically conductive electrode of the semiconductor device, and applying a ground potential to an electrically conductive semiconductor layer of the semiconductor device.
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公开(公告)号:US20180145109A1
公开(公告)日:2018-05-24
申请号:US15857086
申请日:2017-12-28
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Qing Cao , Shu-Jen Han
IPC: H01L27/146 , H01L31/032 , H01L31/0296
CPC classification number: H01L27/14652 , H01L27/14636 , H01L27/14647 , H01L27/14696 , H01L31/0296 , H01L31/032
Abstract: A three-dimensional multispectral imaging sensor and method for forming a three-dimensional multispectral imaging sensor are provided. The three-dimensional multispectral imaging sensor includes a monolithic structure having a plurality of layers. Each of the layers is formed from light detecting materials for detecting light of respective different non-overlapping wavelengths and having respective different bandgaps.
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公开(公告)号:US20180138119A1
公开(公告)日:2018-05-17
申请号:US15850564
申请日:2017-12-21
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Qing Cao , Kangguo Cheng , Zhengwen Li , Fei Liu
IPC: H01L23/525 , H01L29/06 , H01L23/532 , H01L23/367 , H01L23/373 , H01L23/528
CPC classification number: H01L23/525 , H01L21/02115 , H01L21/32053 , H01L21/823437 , H01L23/367 , H01L23/3677 , H01L23/3732 , H01L23/5228 , H01L23/5256 , H01L23/528 , H01L23/53209 , H01L23/5329 , H01L29/0649
Abstract: A semiconductor device includes a first dielectric layer formed on a second dielectric layer and planar contacts formed in the second dielectric layer. The planar contacts are spaced apart to form a gap therebetween. The first dielectric layer includes a thermally conductive dielectric layer and is formed on lateral sides of the planar contacts and in the gap. A resistive element is formed between the planar contacts over the gap and in contact with at least the thermally conductive dielectric layer in the gap.
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公开(公告)号:US20180053733A1
公开(公告)日:2018-02-22
申请号:US15802590
申请日:2017-11-03
Applicant: International Business Machines Corporation
Inventor: Qing Cao , Kangguo Cheng , Zhengwen Li , Fei Liu
CPC classification number: H01L23/57 , H01L21/56 , H01L23/3142 , H01L23/3157 , H01L23/573 , H01L2924/3512
Abstract: A semiconductor chip includes a chip substrate; a self-destructive layer arranged on the chip substrate, the self-destructive layer including a pyrophoric reactant; and a sealant layer arranged on a surface of the self-destructive layer, on sidewalls of the self-destructive layer, and on the chip substrate such that the sealant layer forms a package seal on the semiconductor chip; wherein the pyrophoric reactant ignites spontaneously upon exposure to air.
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公开(公告)号:US20180040515A1
公开(公告)日:2018-02-08
申请号:US15230443
申请日:2016-08-07
Applicant: International Business Machines Corporation
Inventor: Qing Cao , Kangguo Cheng , Zhengwen Li , Fei Liu
IPC: H01L21/8234 , H01L21/8238 , H01L27/088 , H01L21/02 , H01L29/66
CPC classification number: H01L21/823462 , H01L21/0214 , H01L21/02247 , H01L21/02252 , H01L21/28088 , H01L21/28238 , H01L21/823857 , H01L27/088 , H01L29/517 , H01L29/518 , H01L29/66545
Abstract: Method for fabricating semiconductor device comprising: forming a dummy gate on a first nitrided oxide layer and a non-nitrided oxide layer; nitridizing an exposed section of the non-nitrided oxide layer to form a second nitrided oxide layer; forming an interlayer dielectric on the first nitrided oxide layer and the second nitrided oxide layer; removing the dummy gate from the first nitrided oxide layer to form a first opening with the first nitrided oxide layer exposed in the first opening; removing the dummy gate from the non-nitrided oxide layer to form a second opening with a non-nitrided portion of oxide layer exposed in the second opening; removing the non-nitrided portion of the oxide layer; forming a first dielectric layer and first metal gate material in the first opening; and forming a second dielectric layer and second metal gate material in the second opening.
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