公开(公告)号：US09761294B1

公开(公告)日：2017-09-12

申请号：US15185216

申请日：2016-06-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael B. Healy ,  Hillery C. Hunter ,  Saravanan Sethuraman

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1675 ,  G11C7/04 ,  G11C11/1653 ,  G11C11/1673

Abstract: A method for operating a memory system comprises receiving a write request associate with data, decoding an address of the write request, receiving thermal data indicating a temperature at the address of the write request, determining whether the temperature is above a threshold temperature, and writing the data to the address responsive to determining that the temperature is not above the threshold temperature.

公开(公告)号：US20170160937A1

公开(公告)日：2017-06-08

申请号：US15404232

申请日：2017-01-12

Applicant: International Business Machines Corporation

Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary ,  Kyu-hyoun Kim ,  Saravanan Sethuraman ,  Gary A. Tressler

IPC: G06F3/06 ,  G11C16/34

CPC classification number: G06F3/0616 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/0793 ,  G11C5/04 ,  G11C5/141 ,  G11C16/349 ,  G11C16/3495

Abstract: An endurance parameter value of a non-volatile memory included in a non-volatile dual in-line memory module (NVDIMM) can be monitored and compared against a warning threshold value. In response to the endurance parameter exceeding the warning threshold value, a system alert can be generated, within a host system of the NVDIMM, to inform a system user that the NVDIMM is approaching its end-of-life. If the endurance parameter exceeds a replacement threshold value greater than the warning threshold value, an upgrade process can be initiated. The upgrade process can include copying data from the first non-volatile memory to a volatile memory of the NVDIMM and copying, in response to the first non-volatile memory being replaced with a second non-volatile memory, the data from the volatile memory to the second non-volatile memory.

公开(公告)号：US09378104B2

公开(公告)日：2016-06-28

申请号：US14556735

申请日：2014-12-01

Applicant: International Business Machines Corporation

Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary ,  Saravanan Sethuraman ,  Kenneth L. Wright

IPC: G06F12/00 ,  G06F13/00 ,  G06F11/20 ,  G11C29/50 ,  G11C29/00

CPC classification number: G06F11/2058 ,  G06F11/1456 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2069 ,  G06F11/3037 ,  G06F11/3058 ,  G06F2201/84 ,  G11C5/02 ,  G11C7/04 ,  G11C29/028 ,  G11C29/783 ,  G11C29/83 ,  G11C2029/0409 ,  G11C2029/5002

Abstract: A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also includes ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles and forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips. The method also includes forming a second group of memory chips from the plurality of memory chips distinct from the first group of memory chips based on the first ranked list of memory chips. The method also includes pairing a first memory chip from the first group of memory chips and a second memory chip from the second group of memory chips, and mirroring the pairing of memory chips.

公开(公告)号：US20160132259A1

公开(公告)日：2016-05-12

申请号：US14539277

申请日：2014-11-12

Applicant: International Business Machines Corporation

Inventor： Timothy J. Dell ,  Saravanan Sethuraman ,  Diyanesh B.C. Vidyapoornachary

IPC: G06F3/06 ,  G11C29/44

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0635 ,  G06F3/0644 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/1068 ,  G06F11/1666 ,  G06F11/2056 ,  G06F11/2069 ,  G06F11/2087 ,  G06F11/2094 ,  G06F12/1009 ,  G06F2201/805 ,  G06F2201/85 ,  G06F2201/86 ,  G11C29/44 ,  G11C29/52 ,  G11C29/70 ,  G11C29/76 ,  G11C29/886 ,  G11C2029/0409 ,  G11C2029/4402

Abstract: According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that minors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.

公开(公告)号：US09251054B2

公开(公告)日：2016-02-02

申请号：US14227187

申请日：2014-03-27

Applicant: International Business Machines Corporation

Inventor： Edgar R. Cordero ,  Carlos A. Fernandez ,  Joab D. Henderson ,  Jeffrey A. Sabrowski ,  Anuwat Saetow ,  Saravanan Sethuraman

IPC: G06F11/00 ,  G06F12/02 ,  G06F11/10

CPC classification number: G06F12/0238 ,  G06F11/073 ,  G06F11/0793 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/108 ,  G06F2212/251

Abstract: A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.

Abstract translation: 提供了一种方法，系统和计算机程序产品，用于利用双端口动态随机存取存储器（DRAM）配置来实现存储器子系统的增强的可靠性。 DRAM配置包括第一缓冲器和第二缓冲器，每个缓冲器包括有效性计数器。 接收缓冲器的有效性计数器随着来自传送缓冲器的每个相应数据行通过纠错码（ECC），可靠性，可用性和可服务性（RAS）逻辑被验证并递送到接收缓冲器而增加，而有效性计数器 传送缓冲区递减。 基于有效性计数器的相应计数值，从第一缓冲器或第二缓冲器读取或写入数据。

公开(公告)号：US20150370706A1

公开(公告)日：2015-12-24

申请号：US14307648

申请日：2014-06-18

Applicant: International Business Machines Corporation

Inventor： Edgar R. Cordero ,  David M. Daly ,  Robert K. Montoye ,  Saravanan Sethuraman ,  Diyanesh B. Chinnakkonda Vidyapoornachary

IPC: G06F12/08 ,  G06F13/40 ,  G06F9/455 ,  G06F13/16

CPC classification number: G06F12/0811 ,  G06F3/00 ,  G06F9/45558 ,  G06F9/50 ,  G06F12/0833 ,  G06F13/1673 ,  G06F13/4045 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/283 ,  G06F2212/62

Abstract: Apparatus and methods are disclosed that enable the allocation of a cache portion of a memory buffer to be utilized by an on-cache function controller (OFC) to execute processing functions on “main line” data. A particular method may include receiving, at a memory buffer, a request from a memory controller for allocation of a cache portion of the memory buffer. The method may also include acquiring, by an on-cache function controller (OFC) of the memory buffer, the requested cache portion of the memory buffer. The method may further include executing, by the OFC, a processing function on data stored at the cache portion of the memory buffer.

公开(公告)号：US20150179280A1

公开(公告)日：2015-06-25

申请号：US14138838

申请日：2013-12-23

Applicant: International Business Machines Corporation

Inventor： Charles A. Kilmer ,  Warren E. Maule ,  Saravanan Sethuraman

IPC: G11C29/04 ,  G11C29/02 ,  G11C29/00

CPC classification number: G11C29/50004 ,  G11C29/022 ,  G11C29/025 ,  G11C29/70 ,  G11C29/702 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13188 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/014

Abstract: A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.

Abstract translation: 公开了一种用于测试连接到并布置在用于连接缺陷的逻辑芯片的顶部上的多个存储器芯片的堆叠存储器件的方法。 该方法可以包括通过将数据值写入存储器芯片中的第一位置，从第一位置读取数据值，检测第一位错误并记录第一位错误的位数来测试存储器芯片。 该方法还可以包括通过将数据值写入存储器芯片中的第二位置来测试存储器芯片，从存储器芯片中的第二位置读取数据值，检测第二位错误并记录第二位的位数 错误。 该方法还可以包括用备用连接替换与第一和第二位错误共同的连接。

公开(公告)号：US20140355369A1

公开(公告)日：2014-12-04

申请号：US14462620

申请日：2014-08-19

Applicant: International Business Machines Corporation

Inventor： Edgar R. Cordero ,  Timothy J. Dell ,  Girisankar Paulraj ,  Saravanan Sethuraman

IPC: G11C29/04 ,  G11C29/00

CPC classification number: G11C29/04 ,  G06F13/1673 ,  G11C29/70 ,  G11C29/808 ,  G11C2029/0411

Abstract: A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices.

Abstract translation: 一种当存储器件之一失败时，用于继续操作包括第一和第二存储器件的存储器模块的方法和装置。 该方法包括：通过第一存储器模块接收写入操作请求以写入具有第一和第二部分的数据字。 存储器模块可以具有用于分别存储数据字的第一和第二部分的第一存储器设备和第二存储器设备。 确定第一和第二存储器件之一是否不可操作。 如果第一和第二存储器件之一不能操作，则通过将数据字的第一和第二部分写入第一和第二存储器件中的可操作的一个来执行写入操作。

公开(公告)号：US20140317473A1

公开(公告)日：2014-10-23

申请号：US13867207

申请日：2013-04-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Edgar R. Cordero ,  Timothy J. Dell ,  Joab D. Henderson ,  Jeffrey A. Sabrowski ,  Anuwat Saetow ,  Saravanan Sethuraman

IPC: G11C29/08

CPC classification number: G11C29/4401 ,  G06F11/1048 ,  G11C29/42 ,  G11C29/702 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A method, system and computer program product are provided for implementing ECC (Error Correction Codes) redundancy using reconfigurable logic blocks in a computer system. When a fail is detected when reading from memory, it is determined if the incorrect data is in the data or the ECC component of the data. When incorrect data is found in the ECC component of the data, and an actionable threshold is not reached, a predetermined Reliability, Availability, and Serviceability (RAS) action is taken. When the actionable threshold is reached with incorrect data identified in the ECC component of the data, an analysis process is performed to determine if the ECC logic is faulty. When a fail in the ECC logic is detected, the identified ECC failed logic is replaced with a spare block of logic.

Abstract translation: 提供了一种方法，系统和计算机程序产品，用于在计算机系统中使用可重新配置的逻辑块实现ECC（纠错码）冗余。 当从存储器读取时检测到故障时，确定数据中的错误数据是否在数据或ECC组件中。 当在数据的ECC组件中找到不正确的数据，并且没有达到可操作的阈值时，采取预定的可靠性，可用性和可服务性（RAS）动作。 当在数据的ECC组件中识别出不正确的数据达到可操作的阈值时，执行分析处理以确定ECC逻辑是否有故障。 当检测到ECC逻辑中的故障时，所识别的ECC故障逻辑被替换为备用逻辑块。

公开(公告)号：US20140164853A1

公开(公告)日：2014-06-12

申请号：US13707675

申请日：2012-12-07

Applicant: International Business Machines Corporation

Inventor： Edgar R. Cordero ,  Timothy J. Dell ,  Girisankar Paulraj ,  Saravanan Sethuraman

IPC: G11C29/08

CPC classification number: G11C29/08 ,  G06F11/1666 ,  G06F11/2094 ,  G11C5/04 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A method and apparatus for operation of a memory module for storage of a data word is provided. The apparatus includes a memory module having a set of paired memory devices including a first memory device to store a first section of a data word and a second memory device to store a second section of the data word when used in failure free operation. The apparatus may further include a first logic module to perform a write operation by writing the first and second sections of the data word to both the first memory device and the second memory device upon the determination of certain types of failure. The determination may include that a failure exists in the word section storage of either the first or second memory devices but that no failures exist in equivalent locations of word section storage in the two memory devices.

Abstract translation: 提供了用于存储数据字的存储器模块的操作的方法和装置。 该装置包括具有一组成对存储器件的存储器模块，其包括存储数据字的第一部分的第一存储器件和用于无故障操作时存储数据字的第二部分的第二存储器件。 该装置还可以包括第一逻辑模块，用于在确定某些类型的故障时，通过将数据字的第一和第二部分写入第一存储器设备和第二存储器设备来执行写入操作。 该确定可以包括在第一或第二存储器件的单词部分存储中存在故障，但是在两个存储器件中的字段存储的等效位置中不存在故障。