公开(公告)号：US20070205456A1

公开(公告)日：2007-09-06

申请号：US11711616

申请日：2007-02-28

Applicant: Myoung-Jae Lee ,  In-Kyeong Yoo ,  Eun-Hong Lee ,  Jong-Wan Kim ,  Dong-Chul Kim ,  Seung-Eon Ahn

Inventor： Myoung-Jae Lee ,  In-Kyeong Yoo ,  Eun-Hong Lee ,  Jong-Wan Kim ,  Dong-Chul Kim ,  Seung-Eon Ahn

IPC: H01L29/76

CPC classification number: H01L27/1021 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/73

Abstract: A nonvolatile memory device having self-presence diode characteristics, and/or a nonvolatile memory array including the nonvolatile memory device may be provided. The nonvolatile memory device may include a lower electrode, a first semiconductor oxide layer on the lower electrode, a second semiconductor oxide layer on the first semiconductor oxide layer, and/or an upper electrode on the second semiconductor oxide layer.

Abstract translation: 可以提供具有自身存在二极管特性的非易失性存储器件和/或包括非易失性存储器件的非易失性存储器阵列。 非易失性存储器件可以包括下电极，下电极上的第一半导体氧化物层，第一半导体氧化物层上的第二半导体氧化物层，和/或第二半导体氧化物层上的上电极。

公开(公告)号：US20060255392A1

公开(公告)日：2006-11-16

申请号：US11432620

申请日：2006-05-12

Applicant: Choong-Rae Cho ,  In-Kyeong Yoo ,  Yang-Kyu Choi ,  Sung-Il Cho

Inventor： Choong-Rae Cho ,  In-Kyeong Yoo ,  Yang-Kyu Choi ,  Sung-Il Cho

IPC: H01L29/94

CPC classification number: H01L49/003

Abstract: A transistor including a metal-insulation transition material and a method of manufacturing the same. The transistor including a metal-insulator transition material may include a substrate, a insulation layer formed on the substrate, a source region and a drain region separately formed from each other on the insulation layer, a tunneling barrier layer formed on at least one surface of the source region and the drain region, a metal-insulator transition material layer formed on the tunneling barrier layer and the insulation layer, a dielectric layer stacked on the metal-insulator transition material layer, and a gate electrode layer formed on the dielectric layer.

Abstract translation: 一种包括金属绝缘过渡材料的晶体管及其制造方法。 包括金属 - 绝缘体转移材料的晶体管可以包括基板，形成在基板上的绝缘层，在绝缘层上彼此分开形成的源极区域和漏极区域，形成在绝缘层的至少一个表面上的隧道势垒层 源极区域和漏极区域，形成在隧道势垒层和绝缘层上的金属 - 绝缘体转移材料层，堆叠在金属 - 绝缘体转移材料层上的电介质层和形成在电介质层上的栅极电极层。

公开(公告)号：US07002841B2

公开(公告)日：2006-02-21

申请号：US10701436

申请日：2003-11-06

Applicant: In-Kyeong Yoo ,  Wan-jun Park

Inventor： In-Kyeong Yoo ,  Wan-jun Park

IPC: G11C11/34

CPC classification number: H01L27/226 ,  B82Y10/00 ,  G11C11/16

Abstract: An MRAM having improved integration density and ability to use a magnetic tunneling junction (MTJ) layer having a low MR ratio, and methods for manufacturing and driving the same, are disclosed. The MRAM includes a semiconductor substrate having a bipolar junction transistor (BJT) formed thereon, a bit line coupled to an emitter of the BJT, an MTJ layer coupled to the BJT, a word line coupled to the MTJ layer, a plate line coupled to the BJT so as to be spaced apart from the MTJ layer, and an interlayer dielectric formed between components of the MRAM, wherein the MTJ layer is coupled to a base and a collector of the BJT, the plate line is coupled to the collector, and an amplifying unit for amplifying a signal while data is read out from the MTJ layer is coupled to the bit line, thereby allowing precise reading of the data.

Abstract translation: 公开了具有改进的集成密度和使用具有低MR比的磁隧道结（MTJ）层的能力的MRAM及其制造和驱动方法。 MRAM包括其上形成有双极结型晶体管（BJT）的半导体衬底，耦合到BJT的发射极的位线，耦合到BJT的MTJ层，耦合到MTJ层的字线，耦合到 BJT与MTJ层间隔开，以及在MRAM的组件之间形成的层间电介质，其中MTJ层耦合到BJT的基极和集电极，板线耦合到集电器，并且 用于在从MTJ层读出数据时放大信号的放大单元被耦合到位线，从而允许精确地读取数据。

公开(公告)号：US09190103B2

公开(公告)日：2015-11-17

申请号：US13503511

申请日：2010-10-21

Applicant: Chang-Jung Kim ,  In-Kyeong Yoo ,  Ho-Jung Kim ,  Chul-Woo Park

Inventor： Chang-Jung Kim ,  In-Kyeong Yoo ,  Ho-Jung Kim ,  Chul-Woo Park

IPC: G06F12/00 ,  G11B20/00 ,  G06F21/10 ,  G06F21/79 ,  G11C7/24 ,  G06F12/02

CPC classification number: G11B20/00086 ,  G06F12/0246 ,  G06F21/10 ,  G06F21/79 ,  G11B2220/60 ,  G11C7/24

Abstract: Provided are a storage medium, which has a security function, for storing media content and an output apparatus for outputting data stored in the storage medium. The storage medium includes a controller for converting at least one of a position of pins of a connector and a storage position of media content in a memory unit in order to control transmission of the media content in the memory unit to the output apparatus.

Abstract translation: 提供了具有用于存储媒体内容的安全功能的存储介质和用于输出存储在存储介质中的数据的输出设备。 存储介质包括控制器，用于将连接器的引脚的位置和存储器单元中的媒体内容的存储位置中的至少一个转换为控制存储器单元中的媒体内容向输出设备的传输。

公开(公告)号：US07935953B2

公开(公告)日：2011-05-03

申请号：US11979432

申请日：2007-11-02

Applicant: Seung-Eon Ahn ,  In-Kyeong Yoo ,  Young-Soo Joung ,  Young-Kwan Cha ,  Myoung-Jae Lee ,  David Seo ,  Sun-Ae Seo

Inventor： Seung-Eon Ahn ,  In-Kyeong Yoo ,  Young-Soo Joung ,  Young-Kwan Cha ,  Myoung-Jae Lee ,  David Seo ,  Sun-Ae Seo

IPC: H01L45/00 ,  H01L23/62

CPC classification number: G11C13/0007 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: A nonvolatile memory device including a lower electrode, a resistor structure disposed on the lower electrode, a middle electrode disposed on the resistor structure, a diode structure disposed on the middle electrode, and an upper electrode disposed on the diode structure. A nonvolatile memory device wherein the resistor structure includes one resistor and the diode structure includes one diode. An array of nonvolatile memory device as described above. Methods of manufacturing a nonvolatile memory device and an array of nonvolatile memory device.

Abstract translation: 一种非易失性存储器件，包括下电极，设置在下电极上的电阻结构，设置在电阻结构上的中间电极，设置在中间电极上的二极管结构，以及设置在二极管结构上的上电极。 一种非易失性存储器件，其中电阻器结构包括一个电阻器，二极管结构包括一个二极管。 如上所述的非易失性存储器件阵列。 非易失性存储装置的制造方法以及非易失性存储装置的阵列。

公开(公告)号：US20070165434A1

公开(公告)日：2007-07-19

申请号：US11655086

申请日：2007-01-19

Applicant: Jung-Hyun Lee ,  Eun-Hong Lee ,  Sang-Jun Choi ,  In-Kyeong Yoo ,  Myoung-Jae Lee

Inventor： Jung-Hyun Lee ,  Eun-Hong Lee ,  Sang-Jun Choi ,  In-Kyeong Yoo ,  Myoung-Jae Lee

IPC: G11C27/00

CPC classification number: G11C13/003 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/76

Abstract: Resistive memory devices having at least one varistor and methods of operating the same are disclosed. The resistive memory device may include at least one bottom electrode line, at least one top electrode line crossing the at least one bottom electrode line, and at least one stack structure disposed at an intersection of the at least one top electrode line and the at least one bottom electrode line including a varistor and a data storage layer.

Abstract translation: 公开了具有至少一个压敏电阻的电阻式存储器件及其操作方法。 电阻式存储器件可以包括至少一个底部电极线，与至少一个底部电极线交叉的至少一个顶部电极线以及至少一个堆叠结构，该至少一个堆叠结构设置在至少一个顶部电极线和至少一个顶部电极线的交点处 一个底部电极线包括变阻器和数据存储层。

公开(公告)号：US20060180845A1

公开(公告)日：2006-08-17

申请号：US11350867

申请日：2006-02-10

Applicant: Young-Kwan Cha ,  In-Kyeong Yoo ,  Soo-Hwan Jeong

Inventor： Young-Kwan Cha ,  In-Kyeong Yoo ,  Soo-Hwan Jeong

IPC: H01L21/8238 ,  H01L29/76 ,  H01L21/326

CPC classification number: H01L29/42332 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/7882

Abstract: A memory device with a silicon rich oxide layer and a method of manufacturing the same are provided. The memory device with a silicon rich oxide layer may include a semiconductor substrate, source/drain regions formed on the semiconductor substrate, and a gate structure formed on the semiconductor substrate. The gate structure may contact with the source/drain regions and may include a silicon oxide layer with a silicon content greater than that of a silicon oxide layer (SiO2).

Abstract translation: 提供了具有富硅氧化物层的存储器件及其制造方法。 具有富硅氧化物层的存储器件可以包括半导体衬底，形成在半导体衬底上的源极/漏极区域和形成在半导体衬底上的栅极结构。 栅极结构可以与源极/漏极区域接触，并且可以包括具有大于氧化硅层（SiO 2）的硅含量的硅氧化物层。

公开(公告)号：US06740895B2

公开(公告)日：2004-05-25

申请号：US09865607

申请日：2001-05-29

Applicant: In-Kyeong Yoo

Inventor： In-Kyeong Yoo

IPC: H01J3700

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  H01J37/3175 ,  H01J2237/31777

Abstract: A method and apparatus for emission lithography using a patterned emitter wherein, in the apparatus for emission lithography, a pyroelectric emitter or a ferroelectric emitter is patterned using a mask and it is then heated. Upon heating, electrons are not emitted from that part of the emitter covered by the mask, but are emitted from the exposed part of the emitter not covered by the mask so that the shape of the emitter pattern is projected onto the substrate. To prevent dispersion of emitted electron beams, which are desired to be parallel, the electron beams are controlled using a magnet, a direct current magnetic field generator or a deflection system, thereby achieving an exact one-to-one projection or an exact x-to-one projection of the desired pattern etched on the substrate.

Abstract translation: 使用图案化发射器的发射光刻的方法和装置，其中在用于发射光刻的装置中，使用掩模对热电发射体或铁电发射体进行图案化，然后将其加热。 在加热时，电子不会从掩模覆盖的发射体的那部分发射，而是从未被掩模覆盖的发射体的暴露部分发射，使得发射极图案的形状投影到基板上。 为了防止所期望的平行的发射电子束的分散，使用磁体，直流磁场发生器或偏转系统来控制电子束，从而实现精确的一对一投影或精确的x- 在基板上刻蚀所需图案的一对一投影。

公开(公告)号：US06476402B1

公开(公告)日：2002-11-05

申请号：US09619526

申请日：2000-07-19

Applicant: In-Kyeong Yoo

Inventor： In-Kyeong Yoo

IPC: H01J3700

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  H01J37/3175 ,  H01J2237/31777

Abstract: A method and an apparatus for pyroelectric lithography using a patterned emitter is provided. In the apparatus for pyroelectric lithography, a pyroelectric emitter or a ferroelectric emitter is patterned using a mask and it is then heated. Upon heating, electrons are not emitted from that part of the emitter covered by the mask, but are emitted from the exposed part of the emitter not covered by the mask so that the shape of the emitter pattern is projected onto the substrate. To prevent dispersion of emitted electron beams, which are desired to be parallel, the electron beams are controlled using a magnet or a projection system, thereby achieving exact a one-to-one projection or a x-to-one projection of the desired pattern etched on the substrate.

Abstract translation: 提供了一种使用图案化发射器进行热电光刻的方法和装置。 在用于热电光刻的装置中，使用掩模对热电发射体或铁电发射体进行图案化，然后将其加热。 在加热时，电子不会从掩模覆盖的发射体的那部分发射，而是从未被掩模覆盖的发射体的暴露部分发射，使得发射极图案的形状投影到基板上。 为了防止希望平行的发射电子束的分散，使用磁体或投影系统控制电子束，从而精确地实现所需图案的一对一投影或一对一投影 蚀刻在基板上。

公开(公告)号：US5812442A

公开(公告)日：1998-09-22

申请号：US851891

申请日：1997-05-06

Applicant: In-Kyeong Yoo

Inventor： In-Kyeong Yoo

IPC: G11C11/22 ,  G11C11/56 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C11/22 ,  G11C11/5657 ,  G11C11/223

Abstract: A non-volatile ferroelectric memory using a leakage current of a dielectric and a multi-numeration system ferroelectric memory are provided. Unit cells are formed of a transistor. A dielectric or a ferroelectric is used as a gate insulating material. A ferroelectric capacitor is deposited on the upper portion of the gate insulating material and the upper electrode of a ferroelectric capacitor is used as a gate. "Writing" is performed by selecting a material in which the leakage current of the ferroelectric has a negligible value and the leakage current of the dielectric (used as the gate insulating material) is sharply increased. Charges induced between the drain and the source, are increased by applying the voltages which have various levels and identical pulse widths (in the case of "deleting" voltages, having identical levels and various pulse widths) making the leakage current of a various current densities flow through the gate insulating material. Thus, the multi-numeration system information can be stored.

Abstract translation: 提供了使用电介质的漏电流和多计算系统铁电存储器的非挥发性铁电存储器。 单元电池由晶体管形成。 电介质或铁电体用作栅绝缘材料。 铁电电容器沉积在栅绝缘材料的上部，铁电电容器的上电极用作栅极。 通过选择其中铁电体的漏电流具有可忽略的值并且电介质的漏电流（用作栅极绝缘材料）的材料急剧增加来进行“写入”。 通过施加具有各种等级和相同脉冲宽度的电压（在“删除”具有相同电平和各种脉冲宽度的电压的情况下），增加漏极和源极之间的电荷，使得各种电流密度的漏电流 流过栅极绝缘材料。 因此，可以存储多计数系统信息。