公开(公告)号：US20200075530A1

公开(公告)日：2020-03-05

申请号：US16679883

申请日：2019-11-11

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Michael Juerss ,  Konrad Roesl ,  Oliver Eichinger ,  Kok Chai Goh ,  Tobias Schmidt

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/482 ,  H01L29/43 ,  H01L29/45

Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.

公开(公告)号：US10475761B2

公开(公告)日：2019-11-12

申请号：US16126190

申请日：2018-09-10

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Michael Juerss ,  Konrad Roesl ,  Oliver Eichinger ,  Kok Chai Goh ,  Tobias Schmidt

IPC: H01L29/45 ,  H01L29/43 ,  H01L23/482 ,  H01L23/495 ,  H01L23/00

Abstract: A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer.

公开(公告)号：US20140312497A1

公开(公告)日：2014-10-23

申请号：US13866811

申请日：2013-04-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Kok Chai Goh ,  Meng Tong Ong

IPC: H01L23/00 ,  H01L23/28

CPC classification number: H01L24/27 ,  H01L21/561 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/49524 ,  H01L23/60 ,  H01L24/31 ,  H01L24/37 ,  H01L24/40 ,  H01L24/84 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04034 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/24245 ,  H01L2224/37147 ,  H01L2224/37611 ,  H01L2224/4005 ,  H01L2224/40101 ,  H01L2224/40105 ,  H01L2224/40245 ,  H01L2224/84002 ,  H01L2224/84005 ,  H01L2224/848 ,  H01L2224/84801 ,  H01L2224/84897 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/84 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/014

Abstract: A method and apparatus for packaging a semiconductor chip is presented. A semiconductor device includes a chip, a lead, and an encapsulant. The encapsulant includes a stabilization layer, a laminate molding layer connected to the stabilization layer, and a conductive strip connected to the laminate molding layer. The conductive strip electrically connects the contact area of the chip to the lead.

Abstract translation: 提出了一种用于封装半导体芯片的方法和装置。 半导体器件包括芯片，引线和密封剂。 密封剂包括稳定层，连接到稳定层的层压成型层和连接到层压成型层的导电条。 导电带将芯片的接触区域电连接到引线。

公开(公告)号：US20140110835A1

公开(公告)日：2014-04-24

申请号：US13655228

申请日：2012-10-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Meng Tong Ong ,  Thiam Huat Lim ,  Kok Chai Goh

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L25/50 ,  H01L21/78 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/92 ,  H01L24/96 ,  H01L25/072 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/11003 ,  H01L2224/1112 ,  H01L2224/114 ,  H01L2224/1161 ,  H01L2224/11826 ,  H01L2224/13006 ,  H01L2224/13019 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1316 ,  H01L2224/13171 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/13618 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13669 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/27003 ,  H01L2224/2712 ,  H01L2224/274 ,  H01L2224/2761 ,  H01L2224/27826 ,  H01L2224/28105 ,  H01L2224/29006 ,  H01L2224/29019 ,  H01L2224/29155 ,  H01L2224/29157 ,  H01L2224/2916 ,  H01L2224/29171 ,  H01L2224/29562 ,  H01L2224/2957 ,  H01L2224/29611 ,  H01L2224/29618 ,  H01L2224/29639 ,  H01L2224/29644 ,  H01L2224/29655 ,  H01L2224/29669 ,  H01L2224/3003 ,  H01L2224/30181 ,  H01L2224/30505 ,  H01L2224/92133 ,  H01L2224/92135 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/82

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip and a bump. The semiconductor chip has a contact pad on a major surface. The bump is disposed on the contact pad of the semiconductor chip. A solder layer is disposed on sidewalls of the bump.

Abstract translation: 根据本发明的实施例，半导体封装包括半导体芯片和凸块。 半导体芯片在主表面上具有接触焊盘。 凸块设置在半导体芯片的接触焊盘上。 焊料层设置在凸块的侧壁上。