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公开(公告)号:US12255168B2
公开(公告)日:2025-03-18
申请号:US18509357
申请日:2023-11-15
Applicant: Infineon Technologies AG
Inventor: Alexander Heinrich , Michael Juerss , Konrad Roesl , Oliver Eichinger , Kok Chai Goh , Tobias Schmidt
IPC: H01L29/43 , H01L23/00 , H01L23/482 , H01L23/495 , H01L29/45
Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.
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公开(公告)号:US09034751B2
公开(公告)日:2015-05-19
申请号:US14335660
申请日:2014-07-18
Applicant: Infineon Technologies AG
Inventor: Alexander Heinrich , Konrad Roesl , Oliver Eichinger
IPC: H01L21/00 , H01L23/00 , H01L23/495 , H01L23/31
CPC classification number: H01L24/81 , H01L23/3107 , H01L23/49513 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/93 , H01L2224/0345 , H01L2224/03452 , H01L2224/04026 , H01L2224/04042 , H01L2224/0508 , H01L2224/05082 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05184 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/05684 , H01L2224/06181 , H01L2224/27426 , H01L2224/2745 , H01L2224/29018 , H01L2224/29019 , H01L2224/29109 , H01L2224/29111 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/83191 , H01L2224/83203 , H01L2224/83345 , H01L2224/8381 , H01L2224/83898 , H01L2224/83906 , H01L2224/93 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/01327 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/1461 , H01L2924/15787 , H01L2924/181 , H01L2924/351 , H01L2924/00012 , H01L2924/3512 , H01L2924/00 , H01L2924/01023 , H01L2924/0105 , H01L2924/01049 , H01L2224/27 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 μm. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm2 of surface area of the first main surface and heat is applied to the solder material.
Abstract translation: 一种方法包括提供具有沉积在第一主表面上的第一主表面和焊料层的半导体芯片,其中焊料层的粗糙度至少为1μm。 将半导体芯片放置在载体上,半导体芯片的第一主表面面向载体。 将半导体芯片按第一主表面的表面积至少为1牛顿/千克的压力压在载体上,并将热量施加到焊料材料上。
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公开(公告)号:US20140329361A1
公开(公告)日:2014-11-06
申请号:US14335660
申请日:2014-07-18
Applicant: Infineon Technologies AG
Inventor: Alexander Heinrich , Konrad Roesl , Oliver Eichinger
IPC: H01L23/00
CPC classification number: H01L24/81 , H01L23/3107 , H01L23/49513 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/93 , H01L2224/0345 , H01L2224/03452 , H01L2224/04026 , H01L2224/04042 , H01L2224/0508 , H01L2224/05082 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05184 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/05684 , H01L2224/06181 , H01L2224/27426 , H01L2224/2745 , H01L2224/29018 , H01L2224/29019 , H01L2224/29109 , H01L2224/29111 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/83191 , H01L2224/83203 , H01L2224/83345 , H01L2224/8381 , H01L2224/83898 , H01L2224/83906 , H01L2224/93 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/01327 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/1461 , H01L2924/15787 , H01L2924/181 , H01L2924/351 , H01L2924/00012 , H01L2924/3512 , H01L2924/00 , H01L2924/01023 , H01L2924/0105 , H01L2924/01049 , H01L2224/27 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 μm. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm2 of surface area of the first main surface and heat is applied to the solder material.
Abstract translation: 一种方法包括提供具有沉积在第一主表面上的第一主表面和焊料层的半导体芯片,其中焊料层的粗糙度至少为1μm。 将半导体芯片放置在载体上,半导体芯片的第一主表面面向载体。 将半导体芯片按第一主表面的表面积至少为1牛顿/千克的压力压在载体上,并将热量施加到焊料材料上。
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公开(公告)号:US10930614B2
公开(公告)日:2021-02-23
申请号:US15659670
申请日:2017-07-26
Applicant: Infineon Technologies AG
Inventor: Manfred Mengel , Alexander Heinrich , Steffen Orso , Thomas Behrens , Oliver Eichinger , Lim Fong , Evelyn Napetschnig , Edmund Riedl
IPC: H01L23/00 , B23K35/30 , B23K35/26 , B23K35/28 , C22C13/00 , C22C18/00 , C22C18/04 , C22C30/04 , C22C30/06 , H01L23/488 , H01L23/495 , B23K1/00
Abstract: A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.
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公开(公告)号:US20190006311A1
公开(公告)日:2019-01-03
申请号:US16126190
申请日:2018-09-10
Applicant: Infineon Technologies AG
Inventor: Alexander Heinrich , Michael Juerss , Konrad Roesl , Oliver Eichinger , Kok Chai Goh , Tobias Schmidt
IPC: H01L23/00 , H01L29/45 , H01L29/43 , H01L23/482 , H01L23/495
CPC classification number: H01L24/32 , H01L23/4827 , H01L23/49513 , H01L23/49541 , H01L23/49582 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/29 , H01L24/83 , H01L29/43 , H01L29/45 , H01L2224/03438 , H01L2224/0345 , H01L2224/04026 , H01L2224/05083 , H01L2224/05124 , H01L2224/05139 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05669 , H01L2224/08503 , H01L2224/2745 , H01L2224/29082 , H01L2224/29084 , H01L2224/291 , H01L2224/29101 , H01L2224/29105 , H01L2224/29109 , H01L2224/29111 , H01L2224/29113 , H01L2224/29118 , H01L2224/29124 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29166 , H01L2224/29169 , H01L2224/29171 , H01L2224/29184 , H01L2224/32225 , H01L2224/32245 , H01L2224/32503 , H01L2224/32507 , H01L2224/83191 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/8346 , H01L2224/83464 , H01L2224/83469 , H01L2224/83815 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01047 , H01L2924/01048 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/1461 , H01L2924/17738 , H01L2924/17747 , H01L2924/1776 , H01L2924/00014 , H01L2924/01023 , H01L2924/01015 , H01L2924/00
Abstract: A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer.
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公开(公告)号:US20170025375A1
公开(公告)日:2017-01-26
申请号:US15282927
申请日:2016-09-30
Applicant: Infineon Technologies AG
Inventor: Alexander Heinrich , Michael Juerss , Konrad Roesl , Oliver Eichinger , Kok Chai Goh , Tobias Schmidt
IPC: H01L23/00 , H01L23/495
CPC classification number: H01L24/32 , H01L23/4827 , H01L23/49513 , H01L23/49541 , H01L23/49582 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/29 , H01L24/83 , H01L29/43 , H01L29/45 , H01L2224/03438 , H01L2224/0345 , H01L2224/04026 , H01L2224/05083 , H01L2224/05124 , H01L2224/05139 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05669 , H01L2224/08503 , H01L2224/2745 , H01L2224/29082 , H01L2224/29084 , H01L2224/291 , H01L2224/29101 , H01L2224/29105 , H01L2224/29109 , H01L2224/29111 , H01L2224/29113 , H01L2224/29118 , H01L2224/29124 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29166 , H01L2224/29169 , H01L2224/29171 , H01L2224/29184 , H01L2224/32225 , H01L2224/32245 , H01L2224/32503 , H01L2224/32507 , H01L2224/83191 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/8346 , H01L2224/83464 , H01L2224/83469 , H01L2224/83815 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01047 , H01L2924/01048 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/1461 , H01L2924/17738 , H01L2924/17747 , H01L2924/1776 , H01L2924/00014 , H01L2924/01023 , H01L2924/01015 , H01L2924/00
Abstract: An electric device with a multi-layer contact is disclosed. In an embodiment, the electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.
Abstract translation: 公开了具有多层接触的电气设备。 在一个实施例中,电子设备包括载体,连接到载体的半导体衬底以及设置在半导体衬底和载体之间的层系统。 层系统包括设置在半导体衬底上的电接触层。 功能层设置在电接触层上。 粘附层设置在功能层上。 在粘合层和载体之间设置焊料层。
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公开(公告)号:US11842975B2
公开(公告)日:2023-12-12
申请号:US16679883
申请日:2019-11-11
Applicant: Infineon Technologies AG
Inventor: Alexander Heinrich , Michael Juerss , Konrad Roesl , Oliver Eichinger , Kok Chai Goh , Tobias Schmidt
IPC: H01L29/43 , H01L23/00 , H01L29/45 , H01L23/495 , H01L23/482
CPC classification number: H01L24/32 , H01L23/4827 , H01L23/49513 , H01L23/49541 , H01L23/49582 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/29 , H01L24/83 , H01L29/43 , H01L29/45 , H01L2224/0345 , H01L2224/03438 , H01L2224/04026 , H01L2224/05083 , H01L2224/05124 , H01L2224/05139 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05669 , H01L2224/08503 , H01L2224/2745 , H01L2224/291 , H01L2224/29082 , H01L2224/29084 , H01L2224/29101 , H01L2224/29105 , H01L2224/29109 , H01L2224/29111 , H01L2224/29113 , H01L2224/29118 , H01L2224/29124 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29166 , H01L2224/29169 , H01L2224/29171 , H01L2224/29184 , H01L2224/32225 , H01L2224/32245 , H01L2224/32503 , H01L2224/32507 , H01L2224/8346 , H01L2224/83191 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/83464 , H01L2224/83469 , H01L2224/83815 , H01L2924/014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0132 , H01L2924/01046 , H01L2924/01047 , H01L2924/01048 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/10253 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/1461 , H01L2924/1776 , H01L2924/17738 , H01L2924/17747 , H01L2224/291 , H01L2924/014 , H01L2224/05124 , H01L2924/00014 , H01L2224/05139 , H01L2924/00014 , H01L2224/05171 , H01L2924/00014 , H01L2224/05166 , H01L2924/01074 , H01L2224/05184 , H01L2924/00014 , H01L2224/05647 , H01L2924/00014 , H01L2224/05644 , H01L2924/00014 , H01L2224/05639 , H01L2924/00014 , H01L2224/05669 , H01L2924/00014 , H01L2224/29111 , H01L2924/00014 , H01L2224/29118 , H01L2924/00014 , H01L2224/29109 , H01L2924/00014 , H01L2224/29105 , H01L2924/00014 , H01L2224/29113 , H01L2924/00014 , H01L2224/291 , H01L2924/01048 , H01L2224/83447 , H01L2924/00014 , H01L2224/8346 , H01L2924/00014 , H01L2224/83444 , H01L2924/00014 , H01L2224/83439 , H01L2924/00014 , H01L2224/83464 , H01L2924/00014 , H01L2224/83469 , H01L2924/00014 , H01L2224/05655 , H01L2924/01023 , H01L2224/05655 , H01L2924/01015 , H01L2224/83455 , H01L2924/01023 , H01L2224/83455 , H01L2924/01015 , H01L2224/29139 , H01L2924/00014 , H01L2224/29144 , H01L2924/00014 , H01L2924/01327 , H01L2924/00 , H01L2924/13055 , H01L2924/00 , H01L2924/13091 , H01L2924/00 , H01L2924/1461 , H01L2924/00 , H01L2924/1305 , H01L2924/00
Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.
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公开(公告)号:US20200075530A1
公开(公告)日:2020-03-05
申请号:US16679883
申请日:2019-11-11
Applicant: Infineon Technologies AG
Inventor: Alexander Heinrich , Michael Juerss , Konrad Roesl , Oliver Eichinger , Kok Chai Goh , Tobias Schmidt
IPC: H01L23/00 , H01L23/495 , H01L23/482 , H01L29/43 , H01L29/45
Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.
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公开(公告)号:US10475761B2
公开(公告)日:2019-11-12
申请号:US16126190
申请日:2018-09-10
Applicant: Infineon Technologies AG
Inventor: Alexander Heinrich , Michael Juerss , Konrad Roesl , Oliver Eichinger , Kok Chai Goh , Tobias Schmidt
IPC: H01L29/45 , H01L29/43 , H01L23/482 , H01L23/495 , H01L23/00
Abstract: A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer.
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