公开(公告)号：US20240243087A1

公开(公告)日：2024-07-18

申请号：US18620569

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Ryan Joseph Carrazzone ,  Anastasia Arrington ,  Haobo Chen ,  Hongxia Feng ,  Catherine Ka-Yan Mau ,  Kyle Matthew McElhinny ,  Dingying Xu

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L21/4846 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/538 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/1146 ,  H01L2224/1162 ,  H01L2224/11849 ,  H01L2224/1357 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2924/384

Abstract: Systems, apparatus, articles of manufacture, and methods to reduce variation in height of bumps after flow are disclosed. An example apparatus includes a substrate of an integrated circuit package, a first bump on the substrate, a second bump on the substrate, and a third bump on the substrate. The first bump includes first solder on a first metal pad. The first metal pad has a first width and a first thickness. The second bump includes second solder on a second metal pad. The second metal pad has a second width and a second thickness. The second width is less than the first width. The second thickness matches the first thickness. The third bump includes third solder on a third metal pad. The third metal pad has a third width. The third width less than the second width.

公开(公告)号：US20240222304A1

公开(公告)日：2024-07-04

申请号：US18148148

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Jiaqi Wu ,  Haobo Chen ,  Srinivas Pietambaram ,  Bai Nie ,  Gang Duan ,  Kyle Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu

IPC: H01L23/00 ,  H01L23/538

CPC classification number: H01L24/16 ,  H01L23/538 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L25/16

Abstract: Methods and apparatus to reduce solder bump bridging between two substrates. An apparatus includes a first substrate including a first bump and a second bump spaced apart from the first bump, the first bump including a first base, the second bump including a second base; and a second substrate including a third bump and a fourth bump spaced apart from the third bump, the third bump including a third base, the fourth bump including a fourth base, the first base electrically coupled to the third base by first solder, the second base electrically coupled to the fourth base by second solder, the first solder having a first volume, the second solder having a second volume, the first volume less than the second volume.

公开(公告)号：US20240222238A1

公开(公告)日：2024-07-04

申请号：US18091543

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Srinivas Venkata Ramanuja Pietambaram ,  Bai Nie ,  Gang Duan ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/15

CPC classification number: H01L23/49811 ,  H01L23/15 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/81815

Abstract: An integrated circuit device substrate includes a glass substrate with a first major surface comprising a plateau region, a cavity region, and a wall between the plateau region and the cavity region. The first major surface includes thereon a first dielectric region, and the plateau region includes a plurality of conductive pillars. A second major surface of the glass substrate opposite the first major surface includes thereon a second dielectric layer, wherein the second dielectric layer includes at least one dielectric-free window underlying the cavity region.

公开(公告)号：US20240215269A1

公开(公告)日：2024-06-27

申请号：US18086232

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington

IPC: H10B80/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13023

Abstract: An electronic system includes a substrate that includes a glass core layer including a cavity formed through the glass core layer; at least one active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer and a first surface of the at least one active component die, wherein the first buildup layer includes electrically conductive interconnect contacting the at least one active component die and extending to a first surface of the substrate; a second buildup layer contacting a second surface of the glass core layer and a second surface of the at least one active component die; and one or more solder bumps on a second surface of the substrate and contacting the second surface of the at least one active component die.

公开(公告)号：US20240213116A1

公开(公告)日：2024-06-27

申请号：US18069507

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Kyle Arrington ,  Bohan Shan ,  Haobo Chen ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Dingying Xu ,  Xiaoying Guo ,  Bai Nie ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L23/473 ,  H01L23/15 ,  H01L23/467 ,  H01L23/538

CPC classification number: H01L23/473 ,  H01L23/15 ,  H01L23/467 ,  H01L23/5383

Abstract: Methods, systems, apparatus, and articles of manufacture to cool integrated circuit packages having glass substrates are disclosed. An example glass core of an integrated circuit (IC) package disclosed herein includes a fluid inlet to receive a cooling fluid, a fluid outlet, and a channel to fluidly couple the fluid inlet to the fluid outlet, the cooling fluid to flow through the channel from the fluid inlet to the fluid outlet, the channel fluidly isolated from one or more vias extending between a first surface and a second surface of the glass core.

公开(公告)号：US20220399263A1

公开(公告)日：2022-12-15

申请号：US17345912

申请日：2021-06-11

Applicant: Intel Corporation

Inventor： Brandon Christian Marin ,  Tarek A. Ibrahim ,  Karumbu Nathan Meyyappan ,  Valery Ouvarov-Bancalero ,  Dingying Xu

IPC: H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A z-disaggregated integrated circuit package substrate assembly comprises a first substrate component (a coreless patch), a second substrate component (a core patch), and a third substrate component (an interposer). The coreless patch comprises thinner dielectric layers and higher density routing and can comprise an embedded bridge to allow for communication between integrated circuit dies attached to the coreless patch. The core layer acts as a middle layer interconnect between the coreless patch and the interposer and comprises liquid metal interconnects to connect the core patch physically and electrically to the coreless patch and the interposer. Core patch through holes comprise liquid metal plugs. Some through holes can be surrounded by and coaxially aligned with magnetic plugs to provide improved power signal delivery. The interposer comprises thicker dielectric layers and lower density routing. The substrate assembly can reduce cost and provide improved overall yield and electrical performance relative to monolithic substrates.

公开(公告)号：US20170179099A1

公开(公告)日：2017-06-22

申请号：US15401717

申请日：2017-01-09

Applicant: Intel Corporation

Inventor： Chuan Hu ,  Dingying Xu ,  Yoshihiro Tomita

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76838 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27002 ,  H01L2224/27003 ,  H01L2224/27334 ,  H01L2224/2784 ,  H01L2224/29078 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having one or more dies connected to an integrated circuit substrate by an interface layer. In one embodiment, the interface layer may include an anisotropic portion configured to conduct electrical signals in the out-of-plane direction between one or more components, such as a die and an integrated circuit substrate. In another embodiment, the interface layer may be a dielectric or electrically insulating layer. In yet another embodiment, the interface layer may include an anisotropic portion that serves as an interconnect between two components, a dielectric or insulating portion, and one or more interconnect structures that are surrounded by the dielectric or insulating portion and serve as interconnects between the same or other components. Other embodiments may be described and/or claimed.

公开(公告)号：US20240395567A1

公开(公告)日：2024-11-28

申请号：US18323521

申请日：2023-05-25

Applicant: Intel Corporation

Inventor： Jonas G. Croissant ,  Yiqun Bai ,  Dingying Xu ,  Xavier F. Brun ,  Timothy Gosselin ,  Ye Seul Nam ,  Gustavo Arturo Beltran ,  Roberto Serna ,  Jesus S. Nieto Pescador ,  Aris Mercado Orbase

IPC: H01L21/56 ,  G02B6/122 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

Abstract: Integrated circuit (IC) packages with pre-applied underfill in select areas, and methods of forming the same, are disclosed herein. In one example, an IC package includes a package substrate, a first IC die electrically coupled to the package substrate, a second IC die electrically coupled to the first IC die, and a thermoset adhesive that partially fills an area between the first IC die and the second IC die.

公开(公告)号：US20240312865A1

公开(公告)日：2024-09-19

申请号：US18182879

申请日：2023-03-13

Applicant: Intel Corporation

Inventor： Kyle Arrington ,  Bohan Shan ,  Haobo Chen ,  Bai Nie ,  Srinivas Pietambaram ,  Gang Duan ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/3733 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/49877 ,  H01L23/15

Abstract: Methods, systems, apparatus, and articles of manufacture to improve reliability of vias in a glass substrate of an integrated circuit package are disclosed. An example integrated circuit (IC) package substrate includes a glass substrate, a via extending between first and second surfaces of the glass substrate, and a conductive material provided in the via, the conductive material including gallium and silver.

公开(公告)号：US12068222B2

公开(公告)日：2024-08-20

申请号：US17032577

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Mitul Modi ,  Joseph Van Nausdle ,  Omkar Karhade ,  Edvin Cetegen ,  Nicholas Haehn ,  Vaibhav Agrawal ,  Digvijay Raorane ,  Dingying Xu ,  Ziyin Lin ,  Yiqun Bai

IPC: H01L23/42 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/42 ,  H01L21/481 ,  H01L23/3128

Abstract: Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.