公开(公告)号：US09907170B2

公开(公告)日：2018-02-27

申请号：US15037856

申请日：2015-07-01

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Hoay Tien Teoh

IPC: H01R12/70 ,  H01R12/78 ,  H05K1/14 ,  H05K1/02

CPC classification number: H05K1/14 ,  H01R12/7058 ,  H01R12/77 ,  H01R12/78 ,  H01R12/88 ,  H05K1/028 ,  H05K2201/10037 ,  H05K2201/10356

Abstract: A computer system assembly that includes a substrate and a first board mounted on the substrate. A flexible cable is secured to the first board. The computer system assembly further includes a second board mounted on the substrate. The second board includes a FPC connector. The FPC connector includes a body having a channel extending through the body such that the flexible cable may be positioned in the channel and pulled entirely through the body of the FPC connector. The FPC connector further includes a latching mechanism that secures the flexible cable within the channel once the flexible cable is pulled through the FPC connector. The first board and the second board are moved closer together as the flex cable is pulled through the FPC connector before at least one of the first board and the second board is mounted on the substrate.

公开(公告)号：US09606949B1

公开(公告)日：2017-03-28

申请号：US14864019

申请日：2015-09-24

Applicant: INTEL CORPORATION

Inventor： Khang Choong Yong ,  Khai Ern See ,  Amit Kumar Srivastava ,  Jackson Chung Peng Kong ,  Teong Keat Beh ,  Eng Huat Goh

IPC: G06F3/00 ,  G06F13/38 ,  G06F13/40 ,  G06F3/06 ,  G06F11/14

CPC classification number: G06F13/385 ,  G06F3/0634 ,  G06F3/065 ,  G06F3/0673 ,  G06F11/1456 ,  G06F13/4022 ,  G06F13/4081 ,  G06F2201/84

Abstract: A universal interconnection scheme enables system architecture modularization with a hot-pluggable external computing module, such as a PC-on-a-card device using USB type-C technology. With the flexibility to interchange the system computing module with an external module, system performance can be augmented to fulfill the essential needs of the user, whether the system is a portable low-power tablet device, a smartphone, a wearable device such as an Internet of Things device, or a high-performance PC.

公开(公告)号：US20240234303A9

公开(公告)日：2024-07-11

申请号：US17972975

申请日：2022-10-25

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Telesphor Kamgaing ,  Chee Kheong Yoon ,  Chu Aun Lim ,  Eng Huat Goh ,  Jooi Wah Wong ,  Kavitha Nagarajan

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L28/10

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. Power delivery to the device is on the opposite side of the semiconductor devices. The integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.

公开(公告)号：US20230420379A1

公开(公告)日：2023-12-28

申请号：US17848059

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Seok Ling Lim ,  Hazwani Jaffar ,  Yean Ling Soon

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/552 ,  H01L23/66 ,  H01L21/4857 ,  H01L23/49822 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L24/08

Abstract: IC device package routing with metallization features comprising a pseudo-stripline architecture in which the stripline structure is provisioned, in part, by a routing structure separate from routing within the package substrate. A signal route within top metallization level of a package substrate may be electrically shielded, in part, with a metallization feature within a redistribution layer (RDL) of a routing structure that couples one or more IC chips to the package substrate. Accordingly, a package substrate may have fewer levels of metallization, reduced thickness, and/or lower cost while the IC device package still offers excellent EMI performance.

公开(公告)号：US20230178502A1

公开(公告)日：2023-06-08

申请号：US17542107

申请日：2021-12-03

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Poh Boon Khoo

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/05 ,  H01L25/18 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2224/05017 ,  H01L2225/06589 ,  H01L2225/0651

Abstract: Methods and apparatus to reduce thickness of on-package memory architectures are disclosed. An on-package memory architecture includes a memory die; a bonding pad including a first surface and a second surface opposite the first surface; a wire bond electrically coupling the memory die to the first surface of the bonding pad; and a metal stub protruding from the second surface of the bonding pad. The metal stub is to electrically couple with a contact pad on a package substrate of an integrated circuit (IC) package.

公开(公告)号：US11587844B2

公开(公告)日：2023-02-21

申请号：US16306884

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Xi Guo

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065

Abstract: Electronic device package on package (POP) technology is disclosed. A POP can comprise a first electronic device package including a heat source. The POP can also comprise a second electronic device package disposed on the first electronic device package. The second electronic device package can include a substrate having a heat transfer portion proximate the heat source that facilitates heat transfer from the heat source through a thickness of the substrate. The substrate can also have an electronic component portion at least partially about the heat transfer portion that facilitates electrical communication. In addition, the POP can comprise an electronic component operably coupled to the electronic component portion.

公开(公告)号：US20220181289A1

公开(公告)日：2022-06-09

申请号：US17113410

申请日：2020-12-07

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Kyle Davidson ,  Min Suet Lim ,  Kevin Byrd ,  James Wade

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/64 ,  H01L21/56

Abstract: An integrated circuit package may be fabricated by disposing an underfill material between an electronic substrate and an integrated circuit device through an opening in the electronic substrate. In one embodiment, an integrated circuit assembly may include an electronic substrate having a first surface and an opposing second surface, wherein the electronic substrate includes at least one opening extending from the first surface to the second surface. The integrated circuit assembly may further include an integrated circuit device, wherein the integrated circuit device is electrically attached to the electronic substrate with at least one interconnect, and an underfill material may be disposed between the first surface of the electronic substrate and the integrated circuit device, wherein a portion of the underfill material extends into the opening in the electronic substrate.

公开(公告)号：US20220181227A1

公开(公告)日：2022-06-09

申请号：US17677843

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Richard C. Stamey ,  Chu Aun Lim ,  Jimin Yao

IPC: H01L23/31 ,  H01L23/528 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

公开(公告)号：US11322434B2

公开(公告)日：2022-05-03

申请号：US16912595

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Jiun Hann Sir ,  Poh Boon Khoo ,  Eng Huat Goh

IPC: H01R9/00 ,  H01L23/498 ,  H05K3/34 ,  H01L21/48

Abstract: Disclosed embodiments include folded, top-to-bottom interconnects that couple a die side of an integrated-circuit package substrate, to a board as a complement to a ball-grid array for a flip-chip-mounted integrated-circuit die on the die side. The folded, top-to-bottom interconnect is in a molded frame that forms a perimeter around an infield to receive at least one flip-chip IC die. Power, ground and I/O interconnections shunt around the package substrate, and such shunting includes voltage regulation that need not be routed through the package substrate.

公开(公告)号：US11289414B2

公开(公告)日：2022-03-29

申请号：US16098407

申请日：2017-05-16

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/50 ,  H01L23/00 ,  H01L21/48

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package. For instance, in accordance with one embodiment, there is a substrate package having embodied therein a functional silicon die at a top layer of the substrate package; a solder resist layer beneath the functional silicon die of the substrate package; a plurality of die bumps at a bottom surface of the functional silicon die, the plurality of die bumps electrically interfacing the functional silicon die to a substrate through a plurality of solder balls at a top surface of the solder resist layer; each of the plurality of die bumps electrically interfaced to a nickel pad at least partially within the solder resist layer and beneath the solder balls; each of the plurality of die bumps electrically interfaced through the nickel pads to a conductive pad exposed at a bottom surface of the solder resist layer; and in which each of the conductive pads exposed at the bottom surface of the solder resist layer are electrically interfaced to an electrical trace at the substrate of the substrate package. Other related embodiments are disclosed.