公开(公告)号：US10734511B2

公开(公告)日：2020-08-04

申请号：US16077742

申请日：2016-03-31

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Willy Rachmady ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Rafael Rios

IPC分类号： H01L29/778 ,  H01L29/66 ,  H01L29/78 ,  H01L29/205 ,  H01L29/739 ,  H01L29/08

摘要： An embodiment includes a field effect transistor, comprising: a source region comprising a first III-V material doped to a first conductivity type; a drain region comprising a second III-V material doped to a second conductivity type that is opposite the first conductivity type; a gate electrode disposed over a channel region comprising a third III-V material; and a first spacer, between the channel and drain regions, comprising a fourth III-V material having a charge carrier-blocking band offset from the third III-V material. Other embodiments are described herein.

公开(公告)号：US10707319B2

公开(公告)日：2020-07-07

申请号：US15067047

申请日：2016-03-10

申请人： INTEL CORPORATION

发明人： Gilbert Dewey ,  Mark L. Doczy ,  Suman Datta ,  Justin K. Brask ,  Matthew V. Metz

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66

摘要： A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. The method includes depositing a dielectric layer on a substrate, followed by deposition of a capping layer in-situ over the dielectric layer prior to any high temperature processing.

公开(公告)号：US10651313B2

公开(公告)日：2020-05-12

申请号：US16325423

申请日：2016-09-30

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Matthew V. Metz ,  Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Sean T. Ma

IPC分类号： H01L27/088 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/24

摘要： An embodiment includes a transistor comprising: first, second, and third layers each including a group III-V material; a channel included in the second layer, which is between the first and third layers; and a gate having first and second gate portions; wherein (a)(i) the first and third layers are doped, (a)(ii) the channel is between the first and second gate portions and the second gate portion is between the channel and a substrate, (a)(iii) a first axis intersects the first, second, and third layers but not the first gate portion, and (a)(iv) a second axis, parallel to the first axis, intersects the first and second gate portions and the channel. Other embodiments are described herein.

公开(公告)号：US20200098753A1

公开(公告)日：2020-03-26

申请号：US16141000

申请日：2018-09-25

申请人： INTEL CORPORATION

发明人： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani ,  Abhishek A. Sharma

IPC分类号： H01L27/092 ,  H01L29/66 ,  H01L29/267 ,  H01L29/10 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

摘要： Techniques are disclosed for integrating semiconductor oxide materials as alternate channel materials for n-channel devices in integrated circuits. The semiconductor oxide material may have a wider band gap than the band gap of silicon. Additionally or alternatively, the high mobility, wide band gap semiconductor oxide material may have a higher electron mobility than silicon. The use of such semiconductor oxide materials can provide improved NMOS channel performance in the form of less off-state leakage and, in some instances, improved electron mobility as compared to silicon NMOS channels.

公开(公告)号：US10461082B2

公开(公告)日：2019-10-29

申请号：US15577734

申请日：2015-06-26

申请人： Intel Corporation

发明人： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Nadia M. Rahhal-Orabi ,  Tahir Ghani

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/8258 ,  H01L29/10

摘要： Non-silicon fin structures extend from a crystalline heteroepitaxial well material in a well recess of a substrate. III-V finFETs may be formed on the fin structures within the well recess while group IV finFETs are formed in a region of the substrate adjacent to the well recess. The well material may be electrically isolated from the substrate by an amorphous isolation material surrounding pillars passing through the isolation material that couple the well material to a seeding surface of the substrate and trap crystal growth defects. The pillars may be expanded over the well-isolation material by lateral epitaxial overgrowth, and the well recess filled with a single crystal of high quality. Well material may be planarized with adjacent substrate regions. N-type fin structures may be fabricated from the well material in succession with p-type fin structures fabricated from the substrate, or second epitaxial well.

公开(公告)号：US10411007B2

公开(公告)日：2019-09-10

申请号：US15755490

申请日：2015-09-25

申请人： Intel Corporation

发明人： Gilbert Dewey ,  Willy Rachmady ,  Matthew V. Metz ,  Chandra S. Mohapatra ,  Sean T. Ma ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L27/06 ,  H01L29/66 ,  H01L21/8252 ,  H01L29/775 ,  H01L29/06 ,  H01L29/205 ,  H01L21/8258 ,  H01L29/16 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  B82Y10/00 ,  H01L27/092 ,  H01L21/8238

摘要： Monolithic FETs including a channel region in a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a channel region, a semiconductor spacer of a semiconductor material with a band offset relative to the channel material is grown, for example on at least a drain end of the channel region to introduce at least one charge carrier-blocking band offset between the channel semiconductor and a drain region of a third III-V semiconductor material. In some N-type transistor embodiments, the carrier-blocking band offset is a conduction band offset of at least 0.1 eV. A wider band gap and/or a blocking conduction band offset may contribute to reduced gate induced drain leakage (GIDL). Source/drain regions couple electrically to the channel region through the semiconductor spacer, which may be substantially undoped (i.e. intrinsic) or doped. In some embodiments, the semiconductor spacer growth is integrated into a gate-last, source/drain regrowth finFET fabrication process.

公开(公告)号：US20190035921A1

公开(公告)日：2019-01-31

申请号：US16077742

申请日：2016-03-31

申请人： INTEL CORPORATION

发明人： Cheng-Ying Huang ,  Willy Rachmady ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Rafael Rios

IPC分类号： H01L29/778 ,  H01L29/66 ,  H01L29/78 ,  H01L29/205

CPC分类号： H01L29/7786 ,  H01L29/0834 ,  H01L29/205 ,  H01L29/66356 ,  H01L29/66462 ,  H01L29/6656 ,  H01L29/7391 ,  H01L29/78 ,  H01L29/785

摘要： An embodiment includes a field effect transistor, comprising: a source region comprising a first III-V material doped to a first conductivity type; a drain region comprising a second III-V material doped to a second conductivity type that is opposite the first conductivity type; a gate electrode disposed over a channel region comprising a third III-V material; and a first spacer, between the channel and drain regions, comprising a fourth III-V material having a charge carrier-blocking band offset from the third III-V material. Other embodiments are described herein.

公开(公告)号：US20180248028A1

公开(公告)日：2018-08-30

申请号：US15755489

申请日：2015-09-25

申请人： Intel Corporation

发明人： Chandra S. Mohapatra ,  Matthew V. Metz ,  Harold W. Kennel ,  Gilbert Dewey ,  Willy Rachmady ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L29/778 ,  H01L27/092

CPC分类号： H01L29/785 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02455 ,  H01L21/02494 ,  H01L21/02538 ,  H01L21/02639 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/778

摘要： III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A heterojunction between an active region of III-V semiconductor and the substrate provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where the silicon might otherwise behave as an electrically active amphoteric contaminate. In some embodiments, the heterojunction is provided within a base portion of a sub-fin disposed between the substrate and a fin containing a transistor channel region. The heterojunction positioned closer to the substrate than active fin region ensures thermal diffusion of silicon atoms is contained away from the active region of a III-V finFET.

公开(公告)号：US09806195B2

公开(公告)日：2017-10-31

申请号：US15069726

申请日：2016-03-14

申请人： INTEL CORPORATION

发明人： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/49 ,  H04B1/3827

CPC分类号： H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

公开(公告)号：US09698222B2

公开(公告)日：2017-07-04

申请号：US15036406

申请日：2013-12-23

申请人： Intel Corporation

发明人： Benjamin Chu-Kung ,  Sherry R. Taft ,  Van H. Le ,  Sansaptak Dasgupta ,  Seung Hoon Hoon Sung ,  Sanaz K. Gardner ,  Matthew V. Metz ,  Marko Radosavljevic ,  Han Wui Then

IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20

CPC分类号： H01L29/1037 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/66795

摘要： Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.