-
11.发明申请公开(公告)号：US20190050686A1
公开(公告)日：2019-02-14
申请号：US16147663
申请日：2018-09-29
Applicant: Intel Corporation
Inventor： Hassnaa Moustafa , Rita H. Wouhaybi , Nadine L. Dabby , Chaitanya Sreerama , Shekoufeh Qawami
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to add common sense to a human machine interface. Disclosed examples include a human machine interface system that having an actuator to cause artificial intelligence to execute in a virtual execution environment to generate a virtual response to a user input. The system also includes a virtual consequence evaluator to evaluate a virtual consequence that follows from the virtual response, the virtual consequence generated by executing a model of human interactions, and an output device controller to cause an output device to perform a non-virtual response to the user input when the virtual consequence evaluator evaluates the virtual consequence as positive.
-
公开(公告)号：US20190047149A1
公开(公告)日：2019-02-14
申请号：US16145796
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Rita H. Wouhaybi , Shekoufeh Qawami , Hassnaa Moustafa , Chaitanya Sreerama , Nadine L. Dabby
Abstract: Methods and apparatus to train interdependent autonomous machines are disclosed. An example method includes performing an action of a first sub-task of a collaborative task with a first collaborative robot in a robotic cell while a second collaborative robot operates in the robotic cell according to a first recorded action of the second collaborative robot, the first recorded action of the second collaborative robot recorded while a second robot controller associated with the second collaborative robot is trained to control the second collaborative robot to perform a second sub-task of the collaborative task, and training a first robot controller associated with the first collaborative robot based at least on a sensing of an interaction of the first collaborative robot with the second collaborative robot while the action of the first sub-task is performed by the first collaborative robot and the second collaborative robot operates according to the first recorded action.
-
公开(公告)号：US20170372780A1
公开(公告)日：2017-12-28
申请号：US15645990
申请日：2017-07-10
Applicant: Intel Corporation
Inventor： Shekoufeh Qawami , Rajesh Sundaram , Prashant S. Damle , Doyle Rivers , Julie M. Walker
IPC: G11C13/00
CPC classification number: G11C13/0033 , G06F13/1668 , G11C13/0004 , G11C13/004 , G11C13/0069
Abstract: Apparatus, systems, and methods to correct for threshold voltage drift in non-volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non-volatile memory are carried out using the compensated voltage threshold.
-
公开(公告)号：US09703502B2
公开(公告)日：2017-07-11
申请号：US15214005
申请日：2016-07-19
Applicant: Intel Corporation
Inventor： Blaise Fanning , Shekoufeh Qawami , Raymond S. Tetrick , Frank T. Hady
CPC classification number: G06F3/0644 , G06F3/0604 , G06F3/0631 , G06F3/0679 , G06F3/0688 , G06F12/023 , G06F12/0238 , G06F12/0246 , G06F12/08 , G06F12/10 , G06F12/1009 , G06F2212/2024 , G06F2212/205 , G06F2212/7201 , G06F2212/7204 , G11C7/1006 , G11C11/56 , G11C16/00 , Y02D10/13
Abstract: Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.
-
公开(公告)号：US20160188409A1
公开(公告)日：2016-06-30
申请号：US14844843
申请日：2015-09-03
Applicant: Intel Corporation
Inventor： Kiran Pangal , Prashant S. Damle , Rajesh Sundaram , Shekoufeh Qawami , Julie M. Walker , Doyle Rivers
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1044 , G06F11/1048 , G06F11/1068 , H03M13/05 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/27 , H03M13/6508
Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
Abstract translation: 可以通过确定一组存储器阵列的逻辑阵列地址并且至少部分地基于该组内的至少两个存储器阵列的逻辑位置将逻辑阵列地址变换为至少两个唯一阵列地址来减少不可校正的存储器错误 的存储器阵列。 然后使用至少两个唯一的阵列地址分别访问至少两个存储器阵列。
-
Patent Agency Ranking
公开(公告)号：US11584368B2
公开(公告)日：2023-02-21
申请号：US16139805
申请日：2018-09-24
Applicant: Intel Corporation
Inventor： Naissa Conde , Casey Baron , Shekoufeh Qawami , Kooi Chi Ooi , Mengjie Yu
IPC: B60W30/095 , B60W50/14 , G05D1/00
Abstract: Apparatuses and methods for evaluating the risk factors of a proposed vehicle maneuver using remote data are disclosed. In embodiments, a computer-assisted/autonomous driving vehicle communicates with one or more remote data sources to obtain remote sensor data, and process such remote sensor data to determine the risk of a proposed vehicle maneuver. A remote data source may be authenticated and validated, such as by correlation with other remote data sources and/or local sensor data. Correlation may include performing object recognition upon the remote data sources and local sensor data. Risk evaluation is performed on the validated data, and the results of the risk evaluation presented to a vehicle operator or to an autonomous vehicle navigation system.
-
公开(公告)号：US11010061B2
公开(公告)日：2021-05-18
申请号：US16428802
申请日：2019-05-31
Applicant: Intel Corporation
Inventor： Rajesh Sundaram , Albert Fazio , Derchang Kau , Shekoufeh Qawami
Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.
-
18.发明授权公开(公告)号：US10948915B2
公开(公告)日：2021-03-16
申请号：US16118206
申请日：2018-08-30
Applicant: Intel Corporation
Inventor： Shekoufeh Qawami , Casey Baron , Kooi Chi Ooi , Naissa Conde , Mengjie Yu
Abstract: Apparatuses, methods and storage medium associated with computer-assisted or autonomous vehicle incident management, are disclosed herein. In some embodiments, a vehicle incident management system includes a main system controller to determine whether a vehicle hosting the apparatus is involved in a vehicle incident; if so, whether another vehicle is involved; and if so, whether the other vehicle is equipped to exchange incident information; and an inter-vehicle communication subsystem to exchange incident information with the other vehicle, on determination that the vehicle is involved in a vehicle incident involving the other vehicle, and the other vehicle is equipped to exchange incident information. Other embodiments are also described and claimed.
-
19.发明授权公开(公告)号：US10942562B2
公开(公告)日：2021-03-09
申请号：US16146454
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Shekoufeh Qawami , Nageen Himayat , Chaitanya Sreerama , Hassnaa Moustafa , Rita Wouhaybi , Linda Hurd , Nadine L Dabby , Van Le , Gayathri Jeganmohan , Ankitha Chandran
IPC: G06F1/00 , G06F1/3296 , G06F1/3212 , G06F1/324 , G06T15/00 , G06K9/00 , G06N5/04 , G06N20/00 , G06F1/3234 , G06F1/3206
Abstract: Methods and apparatus to manage operation of variable-state computing devices using artificial intelligence are disclosed. An example computing device includes a hardware platform. The example computing device also includes an artificial intelligence (AI) engine to: determine a context of the device; and adjust an operation of the hardware platform based on an expected change in the context of the device. The adjustment modifies at least one of a computational efficiency of the device, a power efficiency of the device, or a memory response time of the device.
-
20.发明授权公开(公告)号：US10930365B2
公开(公告)日：2021-02-23
申请号：US16281559
申请日：2019-02-21
Applicant: Intel Corporation
Inventor： Pavel Poliakov , Andrey Kudryavtsev , Shekoufeh Qawami , Amirali Khatib Zadeh , Monte Klinkenborg
IPC: G11C29/00 , G11C29/38 , G11C29/44 , G06N3/08 , G06N3/04 , G11C11/54 , G11C16/34 , G11C29/56 , G11C29/04
Abstract: In embodiments, a memory controller (MC) includes an output interface, and an execution engine (EE) to identify, based on field test results of a die coupled to the MC, initial test results of the die using an artificial neural network (ANN) trained to identify the die from a set of NVM dies based on initial test results of the set of NVM dies obtained at a time of manufacture of the set of dies. The initial test results include a first useful life prediction and the field test results include a second useful life prediction, and the initial test results are regenerated by the ANN to protect their confidentiality. In embodiments, the MC is further to compare the second useful life prediction with the first useful life prediction, to determine a deviation between the two, and output, via the output interface, the deviation to a user.
-
-
-
-
-
-
-
-
-
Search Results
38
records
(took 0.018 seconds)
