公开(公告)号：US20150213900A1

公开(公告)日：2015-07-30

申请号：US14679574

申请日：2015-04-06

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Kiran Pangal ,  Xin Guo ,  Qingru Meng ,  Hanmant P. Belgal

IPC: G11C16/14 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/102 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3445 ,  G11C29/028 ,  H01L27/115

Abstract: A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range.

公开(公告)号：US10437512B2

公开(公告)日：2019-10-08

申请号：US15394261

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Feng Zhu ,  Aliasgar S. Madraswala ,  Xin Guo

IPC: G06F3/06 ,  G11C29/00 ,  G11C7/14 ,  G11C29/52

Abstract: Examples herein include techniques for flash page retirement following one or more defects in nonvolatile memory. In some examples, a storage controller may retire a first logical page in response to a first read error, and write data to the one or more NVM devices in a program-erase (P/E) cycle without a dummy page being programmed or generated for the retired first logical page. The storage controller may further retire a second logical page in response to a second read error, wherein the first logical page has a higher order than the second logical page in a same physical memory page.

公开(公告)号：US10303571B2

公开(公告)日：2019-05-28

申请号：US14932870

申请日：2015-11-04

Applicant: Intel Corporation

Inventor： Ning Wu ,  Xin Guo ,  Ramkarthik Ganesan ,  Pranav Kalavade ,  Robert Frickey

IPC: G06F11/00 ,  G06F11/20 ,  G06F12/02 ,  G06F11/14 ,  G06F12/0804 ,  G06F12/0868

Abstract: Technology for an apparatus is described. The apparatus can include a first non-volatile memory, a second non-volatile memory to have a write access time faster than the first non-volatile memory, and a memory controller. The memory controller can be configured to detect corrupted data in a selected data region in the first non-volatile memory. The selected data region can be associated with an increased risk of data corruption after data is written from the second non-volatile memory to the first non-volatile memory. Uncorrupted data in the second non-volatile memory that corresponds to the corrupted data in the first non-volatile memory can be identified. Data recovery in the first non-volatile memory can be performed by replacing the corrupted data in the first non-volatile memory with uncorrupted data from the second non-volatile memory.

公开(公告)号：US20190043596A1

公开(公告)日：2019-02-07

申请号：US15838202

申请日：2017-12-11

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Xin Guo ,  Ali Khakifirooz ,  Pranav Kalavade ,  Sagar Upadhyay

IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  G11C16/22

Abstract: Embodiments of the present disclosure may relate to a memory controller that may include a memory interface and a logic circuitry component coupled with the memory interface. In some embodiments, the logic circuitry component is to program one or more NAND cells of a multi-level NAND memory array via the memory interface with a first set of data in a first pass, determine a first temperature of the multi-level NAND memory array in association with the first pass, determine a second temperature of the multi-level NAND memory array, determine a temperature difference between the second temperature and the first temperature, and perform one or more operations based at least in part on a result of the determination of the temperature difference. Other embodiments may be described and/or claimed.

公开(公告)号：US10043573B2

公开(公告)日：2018-08-07

申请号：US15228699

申请日：2016-08-04

Applicant: INTEL CORPORATION

Inventor： Wei Wu ,  Yi Zou ,  Jawad B. Khan ,  Xin Guo

IPC: G11C16/04 ,  G11C11/56 ,  G06F3/06 ,  G11C16/10

Abstract: Provided are a method and apparatus for endurance friendly programming using lower voltage thresholds. A non-volatile memory has storage cells organized as pages programmed using a first number of threshold voltage levels. The storage cells are organized into storage cell groups to which data is written. Each storage cell group is programmed to store a first number of bits of information. A memory controller selects a second number of bits of information from pages less than the first number of bits of information. The memory controller programs the storage cells of the storage cell group using threshold voltage levels from a second number of threshold voltage levels, wherein the second number of threshold voltage levels is less than the first number of threshold voltage levels and comprises a lowest of the first number of threshold voltage levels.

公开(公告)号：US09817600B2

公开(公告)日：2017-11-14

申请号：US15377200

申请日：2016-12-13

Applicant: Intel Corporation

Inventor： Ning Wu ,  Robert E. Frickey ,  Hanmant P. Belgal ,  Xin Guo

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0688 ,  G06F11/1417

Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.

公开(公告)号：US09524774B2

公开(公告)日：2016-12-20

申请号：US14954002

申请日：2015-11-30

Applicant: Intel Corporation

Inventor： Robert E. Frickey ,  Yogesh B. Wakchaure ,  Iwen Chao ,  Xin Guo ,  Kristopher H. Gaewsky

IPC: G11C11/56 ,  G11C16/34 ,  G06F12/02

CPC classification number: G11C11/5642 ,  G06F12/0246 ,  G06F2212/1032 ,  G11C11/5628 ,  G11C16/3404 ,  G11C16/3418 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.

公开(公告)号：US09483185B2

公开(公告)日：2016-11-01

申请号：US14572581

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： David J. Pelster ,  Xin Guo ,  David M. Jones

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0616 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/3034 ,  G06F11/3466 ,  G06F11/3485 ,  G06F2201/81 ,  G06F2201/88

Abstract: The present disclosure is directed to gradual context saving in a data storage device. An example data storage device may comprise at least a non-volatile memory and a control module. The control module may cause context data to be gradually saved to the non-volatile memory based on monitoring write activity to the nonvolatile memory, wherein the context data may correspond to a current state of the data storage device. The control module may cause context data to be saved based on a budget ratio. For example, a budget ratio may compare an amount of total budget consumed (e.g., based a capacity of the data storage device, an amount of data stored in the data storage device, a target time-to-ready for the data storage device, etc.) to an amount of total context data that has already been written to the non-volatile memory.

Abstract translation: 本公开涉及在数据存储设备中逐渐上下文保存。 示例性数据存储设备可以包括至少一个非易失性存储器和控制模块。 控制模块可以基于监视对非易失性存储器的写入活动，使上下文数据逐渐保存到非易失性存储器，其中上下文数据可对应于数据存储设备的当前状态。 控制模块可以基于预算比率来导致上下文数据被保存。 例如，预算比可以比较所消耗的总预算量（例如，基于数据存储设备的容量，存储在数据存储设备中的数据量，数据存储设备的准备时间， 等等）到已经写入非易失性存储器的总上下文数据的量。

公开(公告)号：US20160283143A1

公开(公告)日：2016-09-29

申请号：US14672080

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Xin Guo ,  Feng Zhu ,  Yogesh B. Wakchaure ,  David J. Pelster

IPC: G06F3/06 ,  G11C14/00 ,  G06F11/10

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/108 ,  G11C11/005 ,  G11C16/26 ,  G11C29/52 ,  G11C2029/0411

Abstract: Methods and apparatus related to a rotated planar XOR scheme for Varied-Sector-Size (VSS) enablement in flat indirection systems are described. In one embodiment, non-volatile memory stores user data in a first set of plurality of planes across a plurality of dies and parity data corresponding to the user data in a second set of plurality of planes. The user data in the first set of the plurality of planes across the plurality of dies and the second set of the plurality of planes is rotated to match a mapping of the parity data. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与扁平间接系统中的不同扇形尺寸（VSS）启用的旋转平面XOR方案相关的方法和装置。 在一个实施例中，非易失性存储器将用户数据存储在多个管芯的多个平面的第一组中，并且在第二组多个平面中对应于用户数据的奇偶校验数据。 跨越多个管芯的多个平面的第一组中的用户数据和多个平面中的第二组被旋转以匹配奇偶校验数据的映射。 还公开并要求保护其他实施例。

公开(公告)号：US09208022B2

公开(公告)日：2015-12-08

申请号：US14499003

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Lark-Hoon Leem ,  Kiran Pangal ,  Xin Guo

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/00 ,  G11C29/00 ,  G11C11/56 ,  G11C16/34

CPC classification number: G06F11/1048 ,  G06F11/076 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3495 ,  G11C29/789

Abstract: Examples are given for generating or providing a moving read reference (MRR) table for recovering from a read error of non-volatile memory included in a storage device. In some examples, priorities may be adaptively assigned to entries included in the MRR table. The entries may be ordered for use based on the assigned priorities. In other examples, the MRR table may be ordered for use such that entries with a single MRR value for each read reference value may be used first over entries having multiple MRR values for each read reference value. For these other examples, the MRR table may be adaptively reordered based on which entries were successful or unsuccessful in recovering from a read error but may still be arranged to have single MRR value entries used first for use to recover from another read error.

Abstract translation: 给出了用于生成或提供用于从包括在存储设备中的非易失性存储器的读取错误中恢复的移动读取参考（MRR）表的示例。 在一些示例中，可以将优先级自适应地分配给包括在MRR表中的条目。 可以根据分配的优先级订购条目。 在其他示例中，MRR表可以被排序使用，使得对于每个读取参考值具有单个MRR值的条目可以首先用于对于每个读取参考值具有多个MRR值的条目。 对于这些其他示例，可以基于哪些条目在从读取错误中恢复成功或不成功而自适应地重新排序MRR表，但是仍然可以被布置为具有首先使用的单个MRR值条目用于从另一读取错误中恢复。