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    REGISTRATION MARK FORMATION DURING SIDEWALL IMAGE TRANSFER PROCESS
    11.
    发明申请
    REGISTRATION MARK FORMATION DURING SIDEWALL IMAGE TRANSFER PROCESS 有权
    边框图像传输过程中的注册标志形成

    公开(公告)号：US20160247766A1

    公开(公告)日：2016-08-25

    申请号：US14630715

    申请日：2015-02-25

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： David J. Conklin ,  Allen H. Gabor ,  Sivananda K. Kanakasabapathy ,  Byeong Y. Kim ,  Fee Li Lie ,  Stuart A. Sieg

    IPC分类号： H01L23/544 ,  H01L21/033 ,  H01L21/311

    CPC分类号： H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  G03F9/708 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453

    摘要： Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.

    摘要翻译： 提供了在形成亚光刻结构期间形成诸如对准标记或重叠标记的对准标记的方法。 方法可以包括在半导体层上的硬掩模上形成多个心轴，每个心轴包括与其相邻的间隔物。 选择多个心轴中的至少一个心轴，并且在所述至少一个选定心轴上形成掩模。 离开间隔物去除多个心轴，掩模防止去除至少一个选定的心轴。 去除面具。 第一蚀刻使用间隔物作为亚光刻结构的图案和至少一个选定的心轴和用于对准标记的相邻间隔物，将亚光刻结构和对准标记图案化成硬掩模。 第二蚀刻使用图案化的硬掩模在半导体层中形成次光刻结构，并使用至少一个选定的心轴和图案化的硬掩模在半导体层中形成对准标记。

    Multi-height multi-composition semiconductor fins
    12.
    发明授权
    Multi-height multi-composition semiconductor fins 有权
    多高度多组分半导体鳍片

    公开(公告)号：US09093275B2

    公开(公告)日：2015-07-28

    申请号：US14059797

    申请日：2013-10-22

    申请人： International Business Machines Corporation

    发明人： Brian J. Greene ,  Augustin J. Hong ,  Byeong Y. Kim ,  Dan M. Mocuta

    IPC分类号： H01L21/027 ,  H01L21/02 ,  H01L29/78 ,  H01L29/786 ,  H01L21/18 ,  H01L29/165

    CPC分类号： H01L27/1211 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/182 ,  H01L21/845 ,  H01L29/04 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/785 ,  H01L29/78603

    摘要： A dielectric material layer is formed on a semiconductor-on-insulator (SOI) substrate including a top semiconductor layer containing a first semiconductor material. An opening is formed within the dielectric material layer, and a trench is formed in the top semiconductor layer within the area of the opening by an etch. A second semiconductor material is deposited to a height above the top surface of the top semiconductor layer employing a selective epitaxy process. Another dielectric material layer can be deposited, and another trench can be formed in the top semiconductor layer. Another semiconductor material can be deposited to a different height employing another selective epitaxy process. The various semiconductor material portions can be patterned to form semiconductor fins having different heights and/or different compositions.

    摘要翻译： 在包含第一半导体材料的顶部半导体层的绝缘体上半导体（SOI）基板上形成电介质材料层。 在电介质材料层内形成一个开口，并通过蚀刻在开口区域内的顶部半导体层中形成沟槽。 使用选择性外延工艺将第二半导体材料沉积到顶部半导体层的顶表面上方的高度。 可以沉积另一个介电材料层，并且可以在顶部半导体层中形成另一个沟槽。 可以使用另一选择性外延工艺将另一种半导体材料沉积到不同的高度。 各种半导体材料部分可以被图案化以形成具有不同高度和/或不同组成的半导体鳍片。

    EMBEDDED DRAM MEMORY CELL WITH ADDITIONAL PATTERNING LAYER FOR IMPROVED STRAP FORMATION
    20.
    发明申请
    EMBEDDED DRAM MEMORY CELL WITH ADDITIONAL PATTERNING LAYER FOR IMPROVED STRAP FORMATION 有权
    嵌入式DRAM记忆体与附加图案层，用于改进的形成

    公开(公告)号：US20130228840A1

    公开(公告)日：2013-09-05

    申请号：US13865306

    申请日：2013-04-18

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Kangguo Cheng ,  David M. Dobuzinsky ,  Byeong Y. Kim ,  Munir D. Naeem

    IPC分类号： H01L27/12

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10867 ,  H01L27/1087 ,  H01L29/66181

    摘要： A method of forming a memory cell including forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed.

    摘要翻译： 一种形成包括在层状半导体结构中形成沟槽的存储单元的方法，每个沟槽具有与沟槽之间的分层半导体结构的一部分相邻的内侧壁和与内侧壁相对的外侧壁。 沟槽填充有多晶硅，并且图案化层形成在层状半导体结构之上。 然后通过图案化图案将开口图案化，开口暴露沟槽之间的分层半导体结构的部分，并且仅沿着每个沟槽的内侧壁的多晶硅的垂直部分。 然后蚀刻层状半导体结构。 图案化层防止沿着每个沟槽的外侧壁的多晶硅的第二垂直部分被去除。