公开(公告)号：US07446393B2

公开(公告)日：2008-11-04

申请号：US11710517

申请日：2007-02-26

申请人： Jiutao Li ,  Allen McTeer ,  Gregory Herdt ,  Trung T. Doan

发明人： Jiutao Li ,  Allen McTeer ,  Gregory Herdt ,  Trung T. Doan

IPC分类号： H01L29/20

CPC分类号： C23C14/548 ,  C23C14/0623 ,  C23C14/3464 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143 ,  H01L45/1625

摘要： The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (GexSe1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with the metal. The chalcogenide glass doped with the metal can be used to store data in a memory device. Advantageously, the systems and methods co-sputter the metal and the chalcogenide glass and allow for relatively precise and efficient control of a constituent ratio between the doping metal and the chalcogenide glass. Further advantageously, the systems and methods enable the doping of the chalcogenide glass with a relatively high degree of uniformity over the depth of the formed layer of chalcogenide glass and the metal. Also, the systems and methods allow a metal concentration to be varied in a controlled manner along the thin film depth.

摘要翻译： 本发明涉及允许硫族化物玻璃如硒化锗（Ge x Sb 1-x x）掺杂金属如银的方法和装置， 铜或锌，而不用紫外线（UV）光二极化步骤来用金属掺杂硫族化物玻璃。 掺杂有金属的硫族化物玻璃可用于将数据存储在存储器件中。 有利的是，系统和方法共同溅射金属和硫族化物玻璃，并允许相对精确和有效地控制掺杂金属和硫族化物玻璃之间的组成比。 进一步有利的是，这些系统和方法能够在硫族化物玻璃和金属的形成层的深度上以相对高的均匀度掺杂硫族化物玻璃。 而且，这些系统和方法允许以薄膜深度的受控方式改变金属浓度。

公开(公告)号：US07282440B2

公开(公告)日：2007-10-16

申请号：US10136544

申请日：2002-05-01

申请人： Charles H. Dennison ,  Trung T. Doan

发明人： Charles H. Dennison ,  Trung T. Doan

IPC分类号： H01L21/4763 ,  H01L21/461 ,  H01L21/302

CPC分类号： H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76829 ,  Y10S438/95 ,  Y10S438/97

摘要： A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.

摘要翻译： 提供了在制造集成电路和如此制造的器件的制造中形成垂直触点的工艺。 该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。 该方法包括在基板的表面上形成绝缘层的步骤; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。 在形成多级金属集成电路期间，可以重复上述过程一次或多次。

公开(公告)号：US07253430B2

公开(公告)日：2007-08-07

申请号：US10644685

申请日：2003-08-20

申请人： Trung T. Doan ,  D. Mark Durcan ,  Brent D. Gilgen

发明人： Trung T. Doan ,  D. Mark Durcan ,  Brent D. Gilgen

IPC分类号： H01L47/00 ,  H01L29/00

CPC分类号： H01L45/06 ,  G11C2213/52 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same are disclosed. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

摘要翻译： 公开了一种在硫族化物存储器的电极之间具有减小的接触面积的相位相移型半导体存储器件及其形成方法。 这样的存储器件通过形成从下电极元件的下表面突出的尖端而形成。 在下电极上施加绝缘材料，使得尖端的上表面露出。 硫族化物材料和上电极都形成在尖端顶部，或者尖端被蚀刻到绝缘材料中，并且硫族化物材料和上电极沉积在凹部内。 这允许使存储器单元变得更小并且允许最小化存储器单元的总体功率需求。

公开(公告)号：US07224065B2

公开(公告)日：2007-05-29

申请号：US10933733

申请日：2004-09-02

申请人： Trung T. Doan

发明人： Trung T. Doan

IPC分类号： H01L23/48

CPC分类号： H01L21/76882

摘要： An improved method of forming a semiconductor device structure is disclosed, comprising insertion of a semiconductor wafer into a high-pressure heated chamber and the deposition of a low melting-point aluminum material into a contact hole or via and over an insulating layer overlying a substrate of the wafer. The wafer is heated up to the melting point of the aluminum material and the chamber is pressurized to force the aluminum material into the contact holes or vias and eliminate voids present therein. A second layer of material, comprising a different metal or alloy, which is used as a dopant source, is deposited over an outer surface of the deposited aluminum material layer and allowed to diffuse into the aluminum material layer in order to form a homogenous aluminum alloy within the contact hole or via. A semiconductor device structure made according to the method is also disclosed.

摘要翻译： 公开了一种形成半导体器件结构的改进方法，包括将半导体晶片插入高压加热室中，并将低熔点铝材料沉积到接触孔中或通过覆盖衬底的绝缘层 的晶片。 将晶片加热到铝材料的熔点，并且加压室以迫使铝材料进入接触孔或通孔并消除其中存在的空隙。 第二层材料，包括用作掺杂剂源的不同的金属或合金，沉积在沉积的铝材料层的外表面上，并允许其扩散到铝材料层中以形成均匀的铝合金 在接触孔或通孔内。 还公开了根据该方法制造的半导体器件结构。

公开(公告)号：US07122906B2

公开(公告)日：2006-10-17

申请号：US10767921

申请日：2004-01-29

申请人： Trung T. Doan

发明人： Trung T. Doan

IPC分类号： H01L23/52

CPC分类号： H01L25/50 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/1184 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/81 ,  H01L2224/29099

摘要： A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a second opposing surface thereof. Each of the first and second pluralities of bond pads includes an under-bump metallization (UBM) layer. The singulated semiconductor die is disposed on a semiconductor die site of a semiconductor wafer and a first plurality of conductive bumps electrically couples the first plurality of bond pads of the singulated semiconductor die with a first set of bond pads formed on the semiconductor die site. A second plurality of conductive bumps is disposed on a second set of bond pads of the semiconductor die site. A third plurality of conductive bumps is disposed on the singulated semiconductor die's second plurality of bond pads. The second and third pluralities of conductive bumps are configured for electrical interconnection with an external device.

摘要翻译： 晶片封装包括具有在第一表面上的第一多个接合焊盘和其第二相对表面上的第二多个接合焊盘的单片半导体管芯。 第一和第二多个接合焊盘中的每一个包括凸块下金属化（UBM）层。 单片化半导体管芯设置在半导体晶片的半导体管芯位置上，并且第一多个导电凸块将单片化半导体管芯的第一组接合焊盘与形成在半导体管芯部位上的第一组接合焊盘电耦合。 第二组多个导电凸块设置在半导体管芯部位的第二组接合焊盘上。 第三多个导电凸块设置在单片半导体管芯的第二多个接合焊盘上。 第二和第三多个导电凸块被配置为与外部设备进行电互连。

公开(公告)号：US07112121B2

公开(公告)日：2006-09-26

申请号：US09888084

申请日：2001-06-21

申请人： Whonchee Lee ,  Scott G. Meikle ,  Scott E. Moore ,  Trung T. Doan

发明人： Whonchee Lee ,  Scott G. Meikle ,  Scott E. Moore ,  Trung T. Doan

IPC分类号： B24B1/00

CPC分类号： C25F7/00 ,  B23H5/08 ,  B24B37/042 ,  B24B37/046 ,  B24B37/20 ,  H01L21/32125

摘要： A method and apparatus for removing conductive material from a microelectronic substrate. In one embodiment, the method can include engaging a microelectronic substrate with a polishing surface of a polishing pad, electrically coupling a conductive material of the microelectronic substrate to a source of electrical potential, and oxidizing at least a portion of the conductive material by passing an electrical current through the conductive material from the source of electrical potential. For example, the method can include positioning first and second electrodes apart from a face surface of the microelectronic substrate and disposing an electrolytic fluid between the face surface and the electrodes with the electrodes in fluid communication with the electrolytic fluid. The method can further include removing the portion of conductive material from the microelectronic substrate by moving at least one of the microelectronic and the polishing pad relative to the other. Accordingly, metals such as platinum can be anisotropically removed from the microelectronic substrate. The characteristics of the metal removal can be controlled by controlling the characteristics of the electrical signal applied to the microelectronic substrate, and the characteristics of a liquid disposed between the microelectronic substrate and the polishing pad.

公开(公告)号：US07009298B2

公开(公告)日：2006-03-07

申请号：US10639120

申请日：2003-08-11

申请人： Gurtej S. Sandhu ,  Trung T. Doan ,  Tyler A. Lowrey

发明人： Gurtej S. Sandhu ,  Trung T. Doan ,  Tyler A. Lowrey

IPC分类号： H01L21/302

CPC分类号： H01L21/76855 ,  C23C16/34 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76862

摘要： A contact structure is provided incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor.

摘要翻译： 提供了一种接触结构，其结合使用四 - 二烷基酰氨基 - 钛，Ti（NMe 2 O 3）4 Si 3 O 4的低压化学气相沉积（LPCVD）形成的无定形氮化钛阻挡层。 ，作为前体。

公开(公告)号：US06949464B1

公开(公告)日：2005-09-27

申请号：US09506204

申请日：2000-02-17

申请人： Trung T. Doan

发明人： Trung T. Doan

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76882

摘要： An improved semiconductor device fabrication method comprises insertion of a semiconductor wafer into a high-pressure heated chamber and deposition of a low melting-point aluminum material into a contact hole or via and over an insulating layer overlying a substrate of the wafer. The wafer is heated up to the melting point of the aluminum material and the chamber is pressurized to force the aluminum material into the contact holes or vias and eliminate voids present therein. A second layer of material, comprising a different metal or alloy, which is used as a dopant source, is deposited over an outer surface of the deposited aluminum material layer and allowed to diffuse into the aluminum material layer in order to form a homogenous aluminum alloy within the contact hole or via. A semiconductor device structure made according to the method is also disclosed.

摘要翻译： 改进的半导体器件制造方法包括将半导体晶片插入高压加热室中，并将低熔点铝材料沉积到接触孔中，或者通过覆盖在晶片的衬底上的绝缘层。 将晶片加热到铝材料的熔点，并且加压室以迫使铝材料进入接触孔或通孔并消除其中存在的空隙。 第二层材料，包括用作掺杂剂源的不同的金属或合金，沉积在沉积的铝材料层的外表面上，并允许其扩散到铝材料层中以形成均匀的铝合金 在接触孔或通孔内。 还公开了根据该方法制造的半导体器件结构。

公开(公告)号：US06897467B2

公开(公告)日：2005-05-24

申请号：US10346994

申请日：2003-01-17

申请人： Trung T. Doan ,  D. Mark Durcan ,  Brent D. Gilgen

发明人： Trung T. Doan ,  D. Mark Durcan ,  Brent D. Gilgen

IPC分类号： H01L27/10 ,  H01L27/105 ,  H01L27/24 ,  H01L45/00 ,  H01L47/00

CPC分类号： H01L45/06 ,  G11C2213/52 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same, are disclosed. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

摘要翻译： 公开了一种在硫族化物存储器的电极之间具有减小的接触面积的双相相变半导体存储器件及其形成方法。 这样的存储器件通过形成从下电极元件的下表面突出的尖端而形成。 在下电极上施加绝缘材料，使得尖端的上表面露出。 硫族化物材料和上电极都形成在尖端顶部，或者尖端被蚀刻到绝缘材料中，并且硫族化物材料和上电极沉积在凹部内。 这允许使存储器单元变得更小并且允许最小化存储器单元的总体功率需求。

公开(公告)号：US06793736B2

公开(公告)日：2004-09-21

申请号：US10392940

申请日：2003-03-20

申请人： Gurtej S. Sandhu ,  Trung T. Doan

发明人： Gurtej S. Sandhu ,  Trung T. Doan

IPC分类号： B08B702

CPC分类号： H01L21/67069

摘要： A method for providing a high flux of point of use activated reactive species for semiconductor processing wherein a workpiece is exposed to a gaseous atmosphere containing a transmission gas that is substantially nonattenuating to preselected wavelengths of electromagnetic radiation. A laminar flow of a gaseous constituent is also provided over a substantially planar surface of the workpiece wherein a beam of the electromagnetic radiation is directed into the gaseous atmosphere such that it converges in the laminar flow to provide maximum beam energy in close proximity to the surface of the workpiece, but spaced a finite distance therefrom. The gaseous constituent is dissociated by the beam producing an activated reactive species that reacts with the surface of the workpiece.

摘要翻译： 一种用于提供用于半导体加工的高通量使用激活活性物质的方法，其中工件暴露于含有基本上不衰减到预选的电磁辐射波长的透射气体的气体气氛中。 气体成分的层流还设置在工件的基本上平坦的表面上，其中电磁辐射的束被引导到气态气氛中，使得其在层流中会聚以提供最接近表面的最大束能 的距离。 气体组分由光束解离，产生与工件表面反应的活化反应物质。