公开(公告)号：US11543969B2

公开(公告)日：2023-01-03

申请号：US17332117

申请日：2021-05-27

Applicant: Kioxia Corporation

Inventor： Yoshihisa Kojima ,  Masanobu Shirakawa ,  Kiyotaka Iwasaki

IPC: G06F3/06

Abstract: According to one embodiment, there is provided a nonvolatile memory including a memory cell array, as input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.

公开(公告)号：US11422746B2

公开(公告)日：2022-08-23

申请号：US17002173

申请日：2020-08-25

Applicant: Kioxia Corporation

Inventor： Suguru Nishikawa ,  Yoshihisa Kojima ,  Takehiko Amaki

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G11C11/56

Abstract: A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.

公开(公告)号：US11410735B2

公开(公告)日：2022-08-09

申请号：US17038721

申请日：2020-09-30

Applicant: KIOXIA CORPORATION

Inventor： Kazutaka Takizawa ,  Yoshihisa Kojima ,  Masaaki Niijima

IPC: G11C16/14 ,  G11C16/26 ,  G11C7/04 ,  G11C16/32 ,  G11C16/34 ,  G11C16/30

Abstract: A memory system includes a non-volatile memory chip and a controller. The non-volatile memory chip is capable of determining an erase voltage according to a temperature of the non-volatile memory chip and a correction parameter. The controller is configured to update the correction parameter of the non-volatile memory chip according to temperature information related to the temperature of the non-volatile memory chip. The non-volatile memory chip determines the erase voltage according to the temperature of the non-volatile memory chip and the updated correction parameter received from the controller.

公开(公告)号：US20220115070A1

公开(公告)日：2022-04-14

申请号：US17556663

申请日：2021-12-20

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Marie Takada ,  Tsukasa Tokutomi ,  Yoshihisa Kojima ,  Kiichi Tachi

IPC: G11C16/08 ,  G11C16/34 ,  H01L27/1157 ,  G11C16/12 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  H01L27/11582 ,  G11C16/10

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.

公开(公告)号：US11069413B2

公开(公告)日：2021-07-20

申请号：US16799885

申请日：2020-02-25

Applicant: Kioxia Corporation

Inventor： Suguru Nishikawa ,  Riki Suzuki ,  Yoshihisa Kojima

IPC: G11C16/16 ,  G11C16/26 ,  G06F13/16 ,  G11C16/34 ,  G11C16/12

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller that controls operation of the nonvolatile memory. The nonvolatile memory is configured to receive, from the memory controller, a first command for execution of at least one of an erase operation and a program operation; in response to receiving a second command from the memory controller during execution of a first operation requested by the first command, execute a second operation for suspending the first operation before the first operation reaches a given section; and in response to receiving a third command from the memory controller during the execution of the first operation, suspend the first operation after the given section.

公开(公告)号：US12086439B2

公开(公告)日：2024-09-10

申请号：US18343835

申请日：2023-06-29

Applicant: KIOXIA CORPORATION

Inventor： Shunichi Igahara ,  Toshikatsu Hida ,  Riki Suzuki ,  Takehiko Amaki ,  Suguru Nishikawa ,  Yoshihisa Kojima

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/10

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0253 ,  G06F12/10 ,  G06F2212/1044 ,  G06F2212/657

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

公开(公告)号：US11947400B2

公开(公告)日：2024-04-02

申请号：US18200453

申请日：2023-05-22

Applicant: Kioxia Corporation

Inventor： Yoshihisa Kojima ,  Katsuhiko Ueki

IPC: G06F1/00 ,  G06F1/26 ,  G06F12/02

CPC classification number: G06F1/263 ,  G06F12/0246 ,  G06F2212/2028 ,  G06F2212/205

Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.

公开(公告)号：US11915759B2

公开(公告)日：2024-02-27

申请号：US17556663

申请日：2021-12-20

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Marie Takada ,  Tsukasa Tokutomi ,  Yoshihisa Kojima ,  Kiichi Tachi

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/12 ,  G11C16/26 ,  G11C11/56 ,  G11C16/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/08 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3459 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.

公开(公告)号：US11740965B2

公开(公告)日：2023-08-29

申请号：US17519356

申请日：2021-11-04

Applicant: KIOXIA CORPORATION

Inventor： Shunichi Igahara ,  Yoshihisa Kojima ,  Takehiko Amaki ,  Suguru Nishikawa

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0679 ,  G06F11/1044 ,  G06F11/1056

Abstract: A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.

公开(公告)号：US11733888B2

公开(公告)日：2023-08-22

申请号：US17028087

申请日：2020-09-22

Applicant: Kioxia Corporation

Inventor： Shunichi Igahara ,  Toshikatsu Hida ,  Riki Suzuki ,  Takehiko Amaki ,  Suguru Nishikawa ,  Yoshihisa Kojima

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/02

CPC classification number: G06F3/0634 ,  G06F3/061 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0253 ,  G06F12/10 ,  G06F2212/1044 ,  G06F2212/657

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.