-
公开(公告)号：US20130346772A1
公开(公告)日：2013-12-26
申请号：US13532743
申请日：2012-06-25
IPC分类号： G06F1/32
CPC分类号： G06F1/3262 , G06F1/32 , G06F1/3206 , G06F1/3253 , G06F1/3278 , G06F11/1423 , G06F11/349 , G06F12/0831 , G06F13/1678 , G06F13/38 , G06F13/4018 , G06F13/4027 , G06F2213/0062 , H04B5/0031 , H04L12/4013 , H04L41/0896 , Y02D10/151 , Y02D10/157
摘要： Described herein are embodiments of an apparatus configured for dynamic link width modulation, a system including an apparatus configured for dynamic link width modulation, a method for dynamic link width modulation, and computer-readable media having instructions that, if executed by one or more processors, cause an apparatus to perform a dynamic link width modulation method. An apparatus configured for dynamic link width modulation may include a first counter for determining a length of a queue of packets at a source of a link, a second counter for determining a rate of utilization of the link, and a power control unit configured to modify a width of the link based at least in part on the length of the queue and the rate of utilization. Other embodiments may be described and/or claimed.
摘要翻译： 这里描述的是被配置用于动态链路宽度调制的装置的实施例，包括被配置用于动态链路宽度调制的装置的系统，用于动态链路宽度调制的方法，以及具有指令的计算机可读介质，所述指令如果由一个或多个处理器 使得设备执行动态链路宽度调制方法。 配置用于动态链路宽度调制的装置可以包括用于确定链路源的分组队列的长度的第一计数器，用于确定链路利用率的第二计数器，以及配置为修改链路的功率控制单元 链路的宽度至少部分地基于队列的长度和利用率。 可以描述和/或要求保护其他实施例。
-
公开(公告)号：US07587625B2
公开(公告)日：2009-09-08
申请号：US11357492
申请日：2006-02-16
IPC分类号： G06F11/00
CPC分类号： G06F11/141 , G06F11/106 , G06F11/1666
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for memory replay mechanisms. In some embodiments, the replay logic includes reset logic to reset at least some of the links in a point-to-point memory interconnect. In addition, the replay logic may include a replay queue to store transaction data and a replay controller to initiate a reset if the transaction data indicates a defined transaction response error. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于存储器重放机制的系统，方法和装置。 在一些实施例中，重播逻辑包括复位逻辑以重置点对点存储器互连中的至少一些链路。 此外，如果事务数据指示定义的事务响应错误，则重放逻辑可以包括用于存储事务数据的重播队列和重放控制器来启动复位。 描述和要求保护其他实施例。
-
公开(公告)号：US06615379B1
公开(公告)日：2003-09-02
申请号：US09457255
申请日：1999-12-08
IPC分类号： G01R3128
CPC分类号： G01R31/318544 , G01R31/318502 , G01R31/318547
摘要： Method and apparatus provides for testing a device or system with a pattern generator. A series of predetermined test vectors are stored, and, for at least some of the test vectors, an associated predetermined MISR signature. A test vector is applied to a device or system under test and a gold unit in response to a gating signal, the test vector having an associated MISR determined by simulating the expected result vector. In response thereto, the gold unit and the device or system under test each produce a result vector which are compared to detect errors in the performance of the system or device under test. A MISR signature is generated for the result vector from the gold unit. The MISR signature for the result vector is then compared to the MISR associated with the input test vector. If the signatures do not match, further test vectors are prevented from being applied to the device or system under test. If the signatures match, a gating signal is provided so that additional test vectors are applied to the device or system under test.
摘要翻译： 方法和装置提供了用模式发生器测试装置或系统。 存储一系列预定测试向量，并且对于至少一些测试向量，存在相关联的预定MISR签名。 将测试矢量应用于被测试的设备或系统，并且响应于门控信号应用金单元，测试向量具有通过模拟预期结果向量确定的相关联的MISR。 作为响应，金单元和被测设备或系统都产生与被检测的系统或设备的性能中的错误进行比较的结果向量。 对于金单元的结果向量生成MISR签名。 然后将结果向量的MISR签名与与输入测试向量相关联的MISR进行比较。 如果签名不匹配，则会阻止进一步的测试向量应用于被测设备或系统。 如果签名匹配，则提供门控信号，以便将附加的测试向量应用于被测设备或系统。
-
14.发明授权Apparatus for transferring information between an interrupt producer and an interrupt service environment 失效用于在中断产生器和中断服务环境之间传送信息的装置
公开(公告)号：US5497456A
公开(公告)日：1996-03-05
申请号：US404136
申请日：1995-03-13
CPC分类号： G06F11/261 , G06F11/3656
摘要： A micro processor emulator in which a set of core micro processor registers are the communication interface between an external system and a core-ported memory. The registers are connected to a serial scan port for transfer of information between a halted emulation environment and the external system. The serial port includes a command register that receives a jump address to initiate execution of a software monitor. Two special bits are provided in the command register, one that indicates a break, and one that indicates a Fast Break GO. This provides a break mechanism for a micro processor chip which does not have a dedicated memory bus. This break mechanism is the mechanism by which a halt or an asynchronous break is effected. After a fast break, the Fast Break GO mechanism does the action described by one command, and then immediately goes back to emulation without any external processor intervention.
摘要翻译： 一种微处理器仿真器，其中一组核心微处理器寄存器是外部系统和核心端口存储器之间的通信接口。 寄存器连接到串行扫描端口，用于在暂停的仿真环境和外部系统之间传输信息。 串行端口包括一个命令寄存器，它接收跳转地址以启动软件监视器的执行。 在命令寄存器中提供两个特殊位，一个表示一个中断，一个表示快速跳转GO。 这为不具有专用存储器总线的微处理器芯片提供了中断机制。 这种断开机制是实现停止或异步中断的机制。 快速中断后，快速断点GO机制执行一个命令描述的动作，然后立即返回仿真，无需任何外部处理器干预。
-
15.发明授权公开(公告)号：US08661284B2
公开(公告)日：2014-02-25
申请号：US13741532
申请日：2013-01-15
CPC分类号： G06F1/04 , G11C7/1045 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. In yet another embodiment of the invention, the registered memory module is allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module.
摘要翻译： 一种改善注册内存模块操作的方法和系统。 在本发明的一个实施例中，当登记的存储器模块中的时钟电路被激活时，所登记的存储器模块允许异步读取和写入操作。 在本发明的另一个实施例中，登记的存储器模块允许其时钟电路的启用或禁用，而不会中断其操作。 当注册的存储器模块中的时钟电路被禁用时，可以减少注册的存储器模块的功耗。 在本发明的另一实施例中，允许登记的存储器模块进入或退出异步操作模式，而不进入或退出已注册存储器模块的自刷新或预充电掉电操作模式。
-
公开(公告)号：US20110320839A1
公开(公告)日：2011-12-29
申请号：US12821867
申请日：2010-06-23
CPC分类号： G06F1/3275 , G06F1/3225 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/14 , Y02D10/172
摘要： Described herein are techniques for dynamic memory frequency/voltage scaling to augment existing memory power management techniques and further improve memory power efficiency. Each operating point is defined as an operational state for the memory.
摘要翻译： 这里描述了用于动态存储器频率/电压缩放以增加现有存储器功率管理技术并进一步提高存储器功率效率的技术。 每个操作点被定义为存储器的操作状态。
-
公开(公告)号：US07516349B2
公开(公告)日：2009-04-07
申请号：US11323345
申请日：2005-12-29
申请人： James W. Alexander , Rajat Agarwal , Pete D. Vogt
发明人： James W. Alexander , Rajat Agarwal , Pete D. Vogt
CPC分类号： G06F13/124
摘要： A memory agent may include a first memory channel interface and a second memory channel, both with unidirectional links, and logic to synchronize a signal processed by the first memory channel interface with a signal processed by the second memory channel interface. An embodiment of a method may include synchronizing a signal on a first memory channel with unidirectional links with a signal on a second memory channel with unidirectional links.
摘要翻译： 存储器代理可以包括具有单向链路的第一存储器通道接口和第二存储器通道，以及用于将由第一存储器通道接口处理的信号与由第二存储器通道接口处理的信号同步的逻辑。 一种方法的实施例可以包括使第一存储器通道上的信号与具有单向链路的第二存储器通道上的信号的单向链路同步。
-
公开(公告)号：US06540123B1
公开(公告)日：2003-04-01
申请号：US09702008
申请日：2000-10-30
IPC分类号： B60R900
摘要： A bed extender apparatus adapted for use with a pickup truck bed to functionally enlarge the useable cargo area within the truck bed when a tailgate is in a lowered position. The bed extender includes a center wall which is pivotably mounted to an inner surface of the tailgate, and which can be pivoted into an upright position once the tailgate is moved into a lowered position. A pair of end walls are pivotably secured to opposite ends of the center wall. Each end wall can be pivoted out to a position extending perpendicular to the center wall once the center wall is in its raised or operative position. Each of the end walls can then be secured to an associated one of the vertical walls of the pickup truck bed. A principal advantage of the bed extender is that the end walls and center wall each include a plurality of members which, when the end walls are folded against the center wall, form an extremely compact arrangement which takes up virtually no appreciable cargo space within the pickup truck bed. The bed extender also forms an extremely aerodynamically efficient structure when in use.
摘要翻译： 一种床扩展器装置，适于与卡车车床一起使用，以在后挡板处于降低位置时功能地扩大卡车底盘内的可用货物区域。 床延长器包括可枢转地安装到后挡板的内表面的中心壁，并且一旦后挡板移动到降低位置中，该中心壁可以枢转到直立位置。 一对端壁可枢转地固定在中心壁的相对端。 一旦中心壁处于其升高或操作位置，每个端壁可以枢转到垂直于中心壁延伸的位置。 然后可以将每个端壁固定到皮卡车床的垂直壁中相关联的一个。 床垫延伸器的主要优点是端壁和中心壁各自包括多个构件，当端壁相对于中心壁折叠时，多个构件形成非常紧凑的布置，其在拾取器内几乎不占据明显的货物空间 卡车床。 床用延长器在使用时也形成极其空气动力学有效的结构。
-
19.发明授权Method and apparatus for synchronizing a JTAG test control signal to an on-chip clock signal 失效用于将JTAG测试控制信号同步到片上时钟信号的方法和装置
公开(公告)号：US5434804A
公开(公告)日：1995-07-18
申请号：US175792
申请日：1993-12-29
申请人： Robert Bock , James W. Alexander
发明人： Robert Bock , James W. Alexander
CPC分类号： H04L7/02 , G01R31/318552 , G06F11/261
摘要： A microprocessor is provided with circuitry for receiving JTAG and ICE test control signals through JTAG test ports and for synchronizing the test signals to a chip clock signal. Test signals synchronized to an external JTAG device are processed internally by an ICE of the microprocessor chip once the test signals are synchronized with the chip clock rate. To this end, the microprocessor is provided with a synchronizer which receives the chip clock signal, a JTAG control signal, and a JTAG reset signal, and outputs a synchronized control signal. The synchronizer includes an unclocked SR flip-flop for sampling the JTAG control signal, and two or more DR flip-flops for synchronizing the JTAG control signal to the chip clock signal. The synchronizer may be configured to generate a control signal pulse or a control signal level. The synchronizer is protocol independent, i.e., the clock rate of the JTAG test commands is independent of the chip clock. Hence, no protocol is required to connect the JTAG test command signals to the ICE. In particular, the synchronizer includes an input stage configured for allowing the JTAG control signal to be much slower than the core clock signal or much faster than the core clock signal.
摘要翻译： 微处理器提供有用于通过JTAG测试端口接收JTAG和ICE测试控制信号并将测试信号同步到芯片时钟信号的电路。 一旦测试信号与芯片时钟速率同步，与外部JTAG器件同步的测试信号由微处理器芯片的ICE内部处理。 为此，微处理器设置有同步器，其接收芯片时钟信号，JTAG控制信号和JTAG复位信号，并输出同步的控制信号。 同步器包括用于对JTAG控制信号进行采样的非锁定SR触发器，以及用于使JTAG控制信号与芯片时钟信号同步的两个或多个DR触发器。 同步器可以被配置为产生控制信号脉冲或控制信号电平。 同步器与协议无关，即JTAG测试命令的时钟速率与芯片时钟无关。 因此，不需要协议将JTAG测试命令信号连接到ICE。 特别地，同步器包括被配置为允许JTAG控制信号比核心时钟信号慢得多或比核心时钟信号快得多的输入级。
-
20.发明授权Minimizing the likelihood of slip between the instant a candidate for a break event is generated and the instant a microprocessor is instructed to perform a break, without missing breakpoints 失效最小化在休息事件的候选者之间产生滑动的可能性，并且指示微处理器执行中断的瞬间，而不丢失断点
公开(公告)号：US5383192A
公开(公告)日：1995-01-17
申请号：US996036
申请日：1992-12-23
申请人： James W. Alexander
发明人： James W. Alexander
CPC分类号： G06F11/261
摘要： An in-circuit emulator on an integrated circuit chip having an input pin for externally triggering on-chip break mechanisms. A break logic having an arm input is connected to an instruction pointer counter (IP counter). The break logic matches the IP counter to an instruction execution address. A counter is provided that once started runs a period of time and then shuts itself off, the length of the period of time being equal to the amount of time it takes for the break logic to arm after assertion of the arm input. A break logic control is connected to the input pin activates the arm input in response to signals on the input pin. The break logic control also starts the counter. The break logic control includes means connected to the arm input, to the counter, to the match output, and to the abrupt break input, operative upon the condition that the match output is asserted during the period of time, to inhibit the assertion of the arm input by the break logic control and asserts the abrupt break input to the abrupt break logic.
摘要翻译： 集成电路芯片上的在线仿真器，具有用于外部触发片上断开机制的输入引脚。 具有臂输入的断开逻辑连接到指令指针计数器（IP计数器）。 中断逻辑将IP计数器与指令执行地址进行匹配。 提供了一个计数器，一旦启动运行一段时间，然后自动关闭，该时间段的长度等于断言逻辑在断言手臂输入之后所需的时间量。 断路逻辑控制连接到输入引脚，响应输入引脚上的信号激活臂输入。 中断逻辑控制也启动计数器。 断路逻辑控制包括连接到臂输入，计数器，匹配输出和突发中断输入的装置，该功能在该时间段期间匹配输出被断言的条件下操作，以阻止 通过断开逻辑控制进行臂输入，并断言突发断点输入到突发断点逻辑。
-
-
-
-
-
-
-
-
-
搜索结果
47 条记录 (耗时 0.027 秒)