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    MEMORY DEVICE
    11.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20240282386A1

    公开(公告)日：2024-08-22

    申请号：US18172308

    申请日：2023-02-22

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

    IPC: G11C16/24 ,  G11C16/04

    CPC classification number: G11C16/24 ,  G11C16/0483

    Abstract: A memory device, such as a three-dimensional AND or NOR flash memory includes a memory cell block, multiple first bit line switches, multiple second bit line switches, a first switch, and a second switch. The memory cell block is divided into a first sub memory cell block and a second sub memory cell block. The first bit line switches are respectively coupled to multiple first local bit lines and commonly coupled to a first sub global bit line. The second bit line switches are respectively coupled to multiple second local bit lines and commonly coupled to a second sub global bit line. The first switch is coupled between the first sub global bit line and a global bit line and controlled by a first control signal. The second switch is coupled between the second sub global bit line and the global bit line and controlled by a second control signal.

    3D AND FLASH MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    12.
    发明公开
    3D AND FLASH MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20230337422A1

    公开(公告)日：2023-10-19

    申请号：US17721222

    申请日：2022-04-14

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chih-Wei Hu ,  Teng Hao Yeh

    IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/04

    CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/0483

    Abstract: A 3D AND flash memory device includes a gate stack structure, a channel pillar, a source pillar, a charge storage structure, a first transistor and a second transistor. The gate stack structure is located on a dielectric substrate, wherein the gate stack structure includes a plurality of gate layers and a plurality of insulating layers alternately stacked. The channel pillar extends through the gate stack structure. The source pillar and the drain pillar are disposed in the channel pillar and electrically connected to the channel pillar. The charge storage structure is located between the plurality of gate layers and the channel pillar. The first transistor is located above the gate stack structure and electrically connected to the drain pillar. The second transistor is located above the gate stack structure and electrically connected to the source pillar.

    Three dimensional memory device
    15.
    发明授权
    Three dimensional memory device 有权
    三维记忆装置

    公开(公告)号：US09576976B1

    公开(公告)日：2017-02-21

    申请号：US14966154

    申请日：2015-12-11

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

    IPC: G11C11/40 ,  H01L27/115 ,  H01L23/528 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04

    CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

    Abstract: A 3D memory device includes a multi-layer stacks structure having a plurality of conductive strips and a first, a second, a third and a fourth ridge stack; a first SSL switch, a first GSL switch, a second SSL switch and a second GSL switch respectively disposed on the first, the second the third and the fourth ridge stack; a first U-shaped memory cells string connecting the first SSL switch with the first GSL switch; a second U-shaped memory cells string connecting the second SSL switch with the second GSL switch; a first word lines contact in contact with the conductive strips disposed in the first ridge stack; a second word lines contact in contact with the conductive strips disposed in the second ridge stack; and a third word lines contact in contact with the conductive strips disposed in the third ridge stack and the fourth ridge stack.

    Abstract translation: 3D存储器件包括具有多个导电条和多个第一，第二，第三和第四脊叠层的多层堆叠结构; 分别设置在第一，第二第三和第四脊叠层上的第一SSL开关，第一GSL开关，第二SSL开关和第二GSL开关; 连接第一个SSL交换机和第一个GSL交换机的第一U形存储单元串; 连接第二SSL开关和第二GSL开关的第二U形存储单元串; 第一字线与设置在第一脊叠层中的导电条接触; 第二字线与设置在第二脊叠层中的导电条接触; 并且第三字线与设置在第三脊叠和第四脊叠中的导电条接触。

    3D voltage switching transistors for 3D vertical gate memory array
    16.
    发明授权
    3D voltage switching transistors for 3D vertical gate memory array 有权
    用于3D立体栅极存储器阵列的3D电压开关晶体管

    公开(公告)号：US09478259B1

    公开(公告)日：2016-10-25

    申请号：US14704706

    申请日：2015-05-05

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Lee-Yin Lin

    IPC: G11C5/02 ,  H01L27/115 ,  G11C16/24 ,  G11C16/14 ,  G11C16/26 ,  G11C5/06 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10

    CPC classification number: H01L27/11582 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

    Abstract: The area consumed by switching transistors for a 3D NAND memory array can be reduced with 3D voltage switching transistors with reduced aggregate area in comparison with 2D voltage switching transistors such as transistors in the substrate. The integrated circuit comprises a 3D NAND array of memory transistors; a plurality of bit lines, with different ones of the plurality of bit lines electrically coupled to different parts of the 3D NAND array; and a plurality of transistor pairs with a stack of semiconductor layers. Different layers in the stack of semiconductor layers include different transistor pairs of the plurality of transistor pairs. Each of the plurality of transistor pairs includes first and second transistors with first, second, and third source/drain terminals. The first transistor includes the first and the third source/drain terminals, and the second transistor includes the second and the third source/drain terminals. The first source/drain terminal is electrically coupled to an erase voltage line. The second source/drain terminal is electrically coupled to a corresponding one of a plurality of program/read voltage lines. The third source/drain terminal is electrically coupled to a corresponding one of the plurality of bit lines.

    Abstract translation: 与2D基板中的晶体管等2D电压开关晶体管相比，3D NAND存储器阵列的开关晶体管消耗的面积可以减小，具有减小的聚集面积的3D电压开关晶体管。 集成电路包括存储晶体管的3D NAND阵列; 多个位线，其中多个位线中的不同的位线电耦合到3D NAND阵列的不同部分; 以及具有堆叠半导体层的多个晶体管对。 半导体层堆叠中的不同层包括多个晶体管对的不同晶体管对。 多个晶体管对中的每一个包括具有第一，第二和第三源极/漏极端子的第一和第二晶体管。 第一晶体管包括第一和第三源极/漏极端子，第二晶体管包括第二和第三源极/漏极端子。 第一源极/漏极端子电耦合到擦除电压线。 第二源极/漏极端子电耦合到多个编程/读取电压线中的对应的一个。 第三源极/漏极端子电耦合到多个位线中的对应的一个位线。

    Three-dimensional vertical gate NAND flash memory including dual-polarity source pads
    17.
    发明授权
    Three-dimensional vertical gate NAND flash memory including dual-polarity source pads 有权
    三维垂直门NAND闪存包括双极性源极焊盘

    公开(公告)号：US09324728B2

    公开(公告)日：2016-04-26

    申请号：US14324842

    申请日：2014-07-07

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

    IPC: H01L27/115 ,  G11C16/06 ,  G11C16/04

    CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578

    Abstract: A memory includes a three-dimensional array including a plurality of levels is described. Each level includes a bit line pad, a source line pad, and a plurality of strips of semiconductor material extending between the bit line pad and the source line pad. The source line pad includes at least one n-type region and at least one p-type region. The memory includes word lines coupled to the plurality of strips in the plurality of levels. The memory includes data storage elements between the word lines and the strips of semiconductor material, whereby memory cells are disposed at cross-points of the strips and the word lines. The memory also includes circuitry coupled to the n-type region and the p-type region of the source line pad, configured to selectively enable current flow in the strips extending from the source line pad and one of the n-type region and the p-type region.

    Abstract translation: 描述包括多个级别的三维阵列的存储器。 每个级别包括位线焊盘，源极线焊盘和在位线焊盘和源极线焊盘之间延伸的多个半导体材料条。 源极线焊盘包括至少一个n型区域和至少一个p型区域。 存储器包括耦合到多个级中的多个条的字线。 存储器包括字线和半导体材料条之间的数据存储元件，由此存储单元设置在条和字线的交叉点处。 存储器还包括耦合到源极线焊盘的n型区域和p型区域的电路，其被配置为选择性地实现从源极线焊盘延伸的条带中的电流和n型区域和p 型区域。

    Memory structure and method for manufacturing the same
    18.
    发明授权
    Memory structure and method for manufacturing the same 有权
    内存结构及其制造方法

    公开(公告)号：US09281315B1

    公开(公告)日：2016-03-08

    申请号：US14636261

    申请日：2015-03-03

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Teng-Hao Yeh ,  Yen-Hao Shih ,  Chih-Wei Hu

    IPC: H01L27/105 ,  H01L29/78 ,  H01L29/417 ,  H01L27/115 ,  H01L23/528 ,  H01L21/8239

    CPC classification number: H01L27/11573 ,  H01L21/8239 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A memory structure and a method for manufacturing the same are provided. The memory structure comprises a substrate, stacks, memory layers, a conductive material and conductive lines. The stacks are positioned on the substrate. The stacks are separated from each other by trenches. Each of the stacks comprises alternately stacked conductive stripes and insulating stripes. The memory layers conformally cover the stacks respectively. The conductive material is positioned in the trenches and on the stacks. The conductive material in the trenches forms one or more holes in each of the trenches. The conductive lines are positioned on the conductive material. Each of the conductive lines comprises a first portion and a second portion connected to each other, the first portion extends along a direction perpendicular to an extending direction of the stacks, and the second portion extends along the extending direction of the stacks.

    Abstract translation: 提供了一种存储器结构及其制造方法。 存储器结构包括衬底，堆叠，存储层，导电材料和导电线。 堆叠位于基板上。 堆叠通过沟槽彼此分离。 每个堆叠包括交替堆叠的导电条纹和绝缘条纹。 存储层分别保守地覆盖堆叠。 导电材料位于沟槽和叠层中。 沟槽中的导电材料在每个沟槽中形成一个或多个孔。 导线位于导电材料上。 每个导线包括彼此连接的第一部分和第二部分，第一部分沿着垂直于堆叠的延伸方向的方向延伸，并且第二部分沿着堆叠的延伸方向延伸。

    3D and flash memory device and method of fabricating the same
    20.
    发明授权
    3D and flash memory device and method of fabricating the same 有权

    公开(公告)号：US12156402B2

    公开(公告)日：2024-11-26

    申请号：US17721222

    申请日：2022-04-14

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chih-Wei Hu ,  Teng Hao Yeh

    IPC: H10B41/27 ,  G11C16/04 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

    Abstract: A 3D AND flash memory device includes a gate stack structure, a channel pillar, a source pillar, a charge storage structure, a first transistor and a second transistor. The gate stack structure is located on a dielectric substrate, wherein the gate stack structure includes a plurality of gate layers and a plurality of insulating layers alternately stacked. The channel pillar extends through the gate stack structure. The source pillar and the drain pillar are disposed in the channel pillar and electrically connected to the channel pillar. The charge storage structure is located between the plurality of gate layers and the channel pillar. The first transistor is located above the gate stack structure and electrically connected to the drain pillar. The second transistor is located above the gate stack structure and electrically connected to the source pillar.

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