公开(公告)号：US20150110384A1

公开(公告)日：2015-04-23

申请号：US14274177

申请日：2014-05-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  Hsiang-Chou Liao ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G06T7/00

CPC classification number: G06T7/0006 ,  G06T2207/30148

Abstract: An image inspection method of die to database is provided, and the positions in the to-be-inspected chips within one wafer may be selected. In the method, a plurality of inspection areas in a plurality of positions in the to-be-inspected chips within a wafer are selected, a plurality of raw images of the inspection areas are obtained, and a plurality of locations of the raw images are then decoded. After that, an image extraction is performed on the raw images to obtain a plurality of image contours. Thereafter, the image contours are compared with a design database of the chip in order to obtain a result of a defect inspection, and execute the same thing in whole wafer.

Abstract translation: 提供了一种针对数据库的图像检查方法，并且可以选择在一个晶片内的待检查芯片中的位置。 在该方法中，选择在晶片内的待检查芯片的多个位置中的多个检查区域，获得检查区域的多个原始图像，原始图像的多个位置 然后解码。 之后，对原始图像执行图像提取以获得多个图像轮廓。 此后，将图像轮廓与芯片的设计数据库进行比较，以获得缺陷检查的结果，并在整个晶片中执行相同的事情。

公开(公告)号：US10354924B2

公开(公告)日：2019-07-16

申请号：US15691510

申请日：2017-08-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Jeng-Hwa Liao ,  Zong-Jie Ko ,  Jung-Yu Shieh ,  Ling-Wuu Yang

IPC: H01L21/70 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11548 ,  H01L29/423

Abstract: Provided is a semiconductor memory device including a substrate, a plurality of first isolation structures, and a plurality of second isolation structures. The substrate includes a periphery region and an array region. The first isolation structures are located in the substrate of the periphery region. The second isolation structures are located in the substrate of the array region. A material of the first isolation structures is different from a material of the second isolation structures. A width of each of the first isolation structures is greater than a width of each of the second isolation structures.

公开(公告)号：US09869712B2

公开(公告)日：2018-01-16

申请号：US14694017

申请日：2015-04-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  I-Jen Huang ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G06F17/50 ,  G01R31/28 ,  G01R31/265

CPC classification number: G01R31/2831 ,  G01R31/2653

Abstract: A method for detecting defects of wafer by wafer sort is introduced. In the method, a wafer sort testing apparatus is used to obtain a DTL or ADART result, wherein a plurality of repaired sites in a wafer is highlighted according to the DTL or ADART result. A plurality of physical locations of the repaired sites is then output. An analysis equipment is used to match the physical locations with a graphic data system (GDS) design layout coordinate of the wafer so as to generate a data correlating with defects at the repaired sites.

公开(公告)号：US09244112B2

公开(公告)日：2016-01-26

申请号：US14275437

申请日：2014-05-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Hsiang-Chou Liao ,  Tuung Luoh ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: H01L21/66 ,  G01R31/04 ,  H01J37/22 ,  H01J37/244 ,  H01J37/28 ,  G01R31/305

CPC classification number: G01R31/04 ,  G01R31/305 ,  H01J37/222 ,  H01J37/244 ,  H01J37/28 ,  H01J2237/049 ,  H01J2237/063 ,  H01J2237/221 ,  H01J2237/24592 ,  H01J2237/2594 ,  H01J2237/28 ,  H01J2237/2817 ,  H01L22/12 ,  H01L22/14

Abstract: A method for detecting an electrical defect of contact/via plugs is provided. In the method, the contact/via plugs are monitored by an electron-beam (E-Beam) inspection tool to capture an image with a VC (voltage contrast) difference, and then an image extraction is performed on the image with the VC difference, wherein the image extraction is based on Target gray level/back ground gray level. The extracted image is contrasted with a layout design base to obtain a blind contact or Quasi-blind issue of contact/via plugs. A grayscale value of the VC difference having the blind contact or Quasi-blind issue is compared with a determined range of grayscale value to determine whether the VC difference is abnormal.

Abstract translation: 提供一种用于检测接触/通孔的电气缺陷的方法。 在该方法中，通过电子束（E-Beam）检查工具来监视接触/通孔塞以捕获具有VC（电压对比度）差异的图像，然后对具有VC差异的图像执行图像提取 ，其中所述图像提取基于目标灰度/背景灰度级。 提取的图像与布局设计基础形成对照，以获得接触/通孔插头的盲接或准盲问题。 将具有盲接或准盲问题的VC差的灰阶值与确定的灰度值范围进行比较，以确定VC差异是否异常。

公开(公告)号：US20230326969A1

公开(公告)日：2023-10-12

申请号：US17855300

申请日：2022-06-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Jeng Hwa Liao ,  Zong-Jie Ko ,  Hsing-Ju Lin ,  Jung-Yu Shieh ,  Ling-Wuu Yang

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L29/167

CPC classification number: H01L29/0847 ,  H01L29/7833 ,  H01L29/66598 ,  H01L21/266 ,  H01L21/26586 ,  H01L29/167 ,  H01L21/26513

Abstract: A transistor structure including a substrate, a gate structure, first pocket doped regions, second pocket doped regions, and source/drain extension regions, and source/drain regions is provided. The gate structure is located on the substrate. The first pocket doped regions are located in the substrate aside the gate structure. A dopant of the first pocket doped region includes a group IVA element. The second pocket doped regions are located in the substrate aside the gate structure. A depth of the second pocket doped region is greater than a depth of the first pocket doped region. The source/drain extension regions are located in the first pocket doped regions. The source/drain regions are located in the substrate aside the gate structure. The source/drain extension region is located between the source/drain region and the gate structure.

公开(公告)号：US20190067119A1

公开(公告)日：2019-02-28

申请号：US15691510

申请日：2017-08-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Jeng-Hwa Liao ,  Zong-Jie Ko ,  Jung-Yu Shieh ,  Ling-Wuu Yang

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11548

CPC classification number: H01L21/823481 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02356 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76229 ,  H01L27/11531 ,  H01L27/11548 ,  H01L29/42364

Abstract: Provided is a semiconductor memory device including a substrate, a plurality of first isolation structures, and a plurality of second isolation structures. The substrate includes a periphery region and an array region. The first isolation structures are located in the substrate of the periphery region. The second isolation structures are located in the substrate of the array region. A material of the first isolation structures is different from a material of the second isolation structures. A width of each of the first isolation structures is greater than a width of each of the second isolation structures.

公开(公告)号：US09116108B1

公开(公告)日：2015-08-25

申请号：US14178293

申请日：2014-02-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G01N23/225

CPC classification number: H01L22/20 ,  H01L22/12

Abstract: An electron beam (E beam) inspection optimization is provided, in which a plurality of initial inspection regions in a chip are obtained, wherein a center of each of the initial inspection regions is a defect point. Thereafter, reset inspection regions are regenerated without overlap, wherein each of the reset inspection regions is within a scope covered by a field of view (FOV) and the scope contains at least one of the defect points. Afterwards, a center of the reset inspection region is transferred into an inspection center, and then an E beam inspection is performed on the inspection center.

Abstract translation: 提供了一种电子束（E光束）检查优化，其中获得了芯片中的多个初始检查区域，其中每个初始检查区域的中心是缺陷点。 此后，复位检查区域不重叠地再生，其中每个复位检查区域在由视场（FOV）覆盖的范围内，并且范围包含至少一个缺陷点。 然后，将复位检查区域的中心转移到检查中心，然后在检查中心进行E光束检查。

公开(公告)号：US20150226687A1

公开(公告)日：2015-08-13

申请号：US14178293

申请日：2014-02-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G01N23/225

CPC classification number: H01L22/20 ,  H01L22/12

Abstract: An electron beam (E beam) inspection optimization is provided, in which a plurality of initial inspection regions in a chip are obtained, wherein a center of each of the initial inspection regions is a defect point. Thereafter, reset inspection regions are regenerated without overlap, wherein each of the reset inspection regions is within a scope covered by a field of view (FOV) and the scope contains at least one of the defect points. Afterwards, a center of the reset inspection region is transferred into an inspection center, and then an E beam inspection is performed on the inspection center.

Abstract translation: 提供了一种电子束（E光束）检查优化，其中获得芯片中的多个初始检查区域，其中每个初始检查区域的中心是缺陷点。 此后，复位检查区域不重叠地再生，其中每个复位检查区域在由视场（FOV）覆盖的范围内，并且范围包含至少一个缺陷点。 然后，将复位检查区域的中心转移到检查中心，然后在检查中心进行E光束检查。

公开(公告)号：US20150213172A1

公开(公告)日：2015-07-30

申请号：US14165043

申请日：2014-01-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  Hsiang-Chou Liao ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G06F17/50 ,  G01Q30/02

CPC classification number: G06F17/5045 ,  G02B21/002 ,  H01J37/28 ,  H01J2237/221 ,  H01J2237/2817

Abstract: A method for measuring a surface structure of a chip or a wafer is provided that includes obtaining an image of the surface structure of the chip, and then performing an image extraction on the image to convert the extracted image into a first circuit design file. A standard image is selected to convert into a second circuit design file, and then the standard image and at least one target in the image are compared to obtain a difference therebetween. According to the difference, at least one data of the surface structure may be made, wherein the data is selected from one of line edge roughness (LER), line width roughness (LWR), contact edge roughness (CER), critical dimension (CD), bias, 3 sigma, maximum, minimum, etc. and repeating defect.

Abstract translation: 提供了一种用于测量芯片或晶片的表面结构的方法，其包括获得芯片的表面结构的图像，然后对图像执行图像提取以将提取的图像转换为第一电路设计文件。 选择标准图像以转换为第二电路设计文件，然后比较图像中的标准图像和至少一个目标，以获得它们之间的差异。 根据差异，可以进行表面结构的至少一个数据，其中数据从线边缘粗糙度（LER），线宽粗糙度（LWR），接触边缘粗糙度（CER），临界尺寸（CD） ），偏置，3西格玛，最大值，最小值等，并重复缺陷。

公开(公告)号：US08735958B1

公开(公告)日：2014-05-27

申请号：US13728783

申请日：2012-12-27

Applicant: Macronix International Co., Ltd.

Inventor： Chun Ling Chiang ,  Wen-Ming Chang ,  Chun-Ming Cheng ,  Ling-Wuu Yang ,  Kuang-Chao Chen

IPC: H01L29/76 ,  H01L29/788 ,  G11C11/34 ,  H01L21/28 ,  H01L29/51 ,  G11C16/04

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7883

Abstract: A blocking semiconductor layer minimizes penetration of implant species into a semiconductor layer beneath the blocking semiconductor layer. The blocking semiconductor layer may have grains with relatively fine or small grain sizes and/or may have a dopant in a relatively low concentration to minimize penetration of implant species into the semiconductor layer beneath the blocking semiconductor layer.

Abstract translation: 阻挡半导体层将植入物种的穿透最小化到阻挡半导体层下方的半导体层中。 阻挡半导体层可具有相对较细或晶粒尺寸较小的晶粒和/或可具有相对较低浓度的掺杂剂，以最小化植入物种进入阻挡半导体层下方的半导体层的穿透。