公开(公告)号：US20200167229A1

公开(公告)日：2020-05-28

申请号：US16776600

申请日：2020-01-30

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Ali Mohammadzadeh

IPC: G06F11/10 ,  G11C11/56 ,  G11C16/28 ,  G11C16/10 ,  G11C16/08 ,  G11C8/12

Abstract: The present disclosure relates to partially written superblock treatment. An example apparatus includes a memory device operable as a multiplane memory resource including blocks organized as superblocks. The memory device is configured to maintain, internal to the memory device, included in a status of an open superblock, a page indicator corresponding to a last written page of the open superblock. The memory device is further configured, responsive to receipt, from a controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request.

公开(公告)号：US20190332284A1

公开(公告)日：2019-10-31

申请号：US16506020

申请日：2019-07-09

Applicant: Micron Technology, Inc.

Inventor： Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Dheeraj Srinivasan ,  Terry M. Grunzke

IPC: G06F3/06 ,  G06F12/0811

Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.

公开(公告)号：US20190056989A1

公开(公告)日：2019-02-21

申请号：US15677736

申请日：2017-08-15

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Ali Mohammadzadeh

IPC: G06F11/10 ,  G11C11/56

CPC classification number: G06F11/1012 ,  G06F11/1068 ,  G11C8/12 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/102 ,  G11C16/28 ,  G11C29/021 ,  G11C29/028 ,  G11C2211/5634 ,  G11C2211/5641 ,  H03M13/37

Abstract: The present disclosure relates to partially written superblock treatment. An example apparatus includes a memory device operable as a multiplane memory resource including blocks organized as superblocks. The memory device is configured to maintain, internal to the memory device, included in a status of an open superblock, a page indicator corresponding to a last written page of the open superblock. The memory device is further configured, responsive to receipt, from a controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request.

公开(公告)号：US10120604B1

公开(公告)日：2018-11-06

申请号：US15621448

申请日：2017-06-13

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Ali Mohammadzadeh

IPC: G06F3/06 ,  G06F12/0811 ,  G11C11/56 ,  G11C16/10

Abstract: Apparatuses and methods for performing buffer operations in memory are provided. An example apparatus can include an array of memory cells, a page buffer, and a controller. The page buffer can be configured to store a number of pages of data in respective caches of the page buffer. The controller can be configured to program the number of pages of data to a first group of cells in the array. The programming operation can include programming the first group of cells to target states encoded with respective data patterns. The programming operation can include incrementally releasing a first of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular first one of the target states, and a second of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular second one of the target states.

公开(公告)号：US12204422B2

公开(公告)日：2025-01-21

申请号：US18143937

申请日：2023-05-05

Applicant: Micron Technology, Inc.

Inventor： Lu Tong ,  Ashish Ghai ,  Chai Chuan Yao ,  Ekamdeep Singh ,  Lakshmi Kalpana Vakati ,  Sheng Huang Lee ,  Matthew Ivan Warren ,  Dheeraj Srinivasan ,  Jeffrey Ming-Hung Tsai

IPC: G06F11/20 ,  G06F3/06

Abstract: Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. In response to determining at least a portion of a first memory block passed a program verify operation associated with a last programming level of the set of programming levels, the control logic executes a first program sub-operation to terminate the programming operation with respect to a first subset of one or more memory planes of the set of memory planes that passed the program verify operation associated with the last programming level and identify a second subset of one or more memory planes that failed the program verify operation associated with the last programming level. The control logic executes a second program sub-operation to apply a trim set to the second subset of one or more memory planes that failed the program verify operation of the last programming level.

公开(公告)号：US20240412787A1

公开(公告)日：2024-12-12

申请号：US18733377

申请日：2024-06-04

Applicant: Micron Technology, Inc.

Inventor： Edric Goh ,  Dheeraj Srinivasan

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: A memory device can include a memory array including a plurality of memory cells coupled to a control logic. The control logic is to initiate a program operation on one or more memory cells of a first segment of the memory array, wherein the program operation comprises a first calibration phase. The control logic can also read a first stored value corresponding to a first voltage applied during a second calibration phase for a second segment of the memory array, the second calibration phase before the first calibration phase. The control logic can further read a second stored value corresponding to an offset value associated with the first voltage. Additionally, the control logic can determine a second voltage for application during the calibration phase responsive to reading the first stored value and the second stored value.

公开(公告)号：US20240071521A1

公开(公告)日：2024-02-29

申请号：US18228291

申请日：2023-07-31

Applicant: Micron Technology, Inc.

Inventor： Dung Viet Nguyen ,  Patrick R. Khayat ,  Sivagnanam Parthasarathy ,  Zhengang Chen ,  Dheeraj Srinivasan

IPC: G11C16/26 ,  G11C16/32 ,  G11C29/52

CPC classification number: G11C16/26 ,  G11C16/32 ,  G11C29/52

Abstract: Described are memory devices producing metadata characterizing the applied read voltage level with respect to voltage distributions. An example memory sub-system comprises: a memory device comprising a plurality of memory cells; and a controller coupled to the memory device, the controller to perform operations comprising: performing, using a read voltage level, a read strobe with respect to a subset of the plurality of memory cells; and receiving, from the memory device, one or more metadata values characterizing the read voltage level with respect to threshold voltage distributions of the subset of the plurality of memory cells, wherein the one or more metadata values reflect a conductive state of one or more bitlines connected to the subset of the plurality of memory cells.

公开(公告)号：US11915758B2

公开(公告)日：2024-02-27

申请号：US18095049

申请日：2023-01-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hao T. Nguyen ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Dheeraj Srinivasan ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Aaron S. Yip ,  Yoshihiko Kamata

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459 ,  G11C11/5621 ,  G11C11/5671

Abstract: Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.

公开(公告)号：US20240006001A1

公开(公告)日：2024-01-04

申请号：US18369479

申请日：2023-09-18

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Dheeraj Srinivasan

IPC: G11C16/34 ,  G11C16/26 ,  G11C7/10 ,  G11C16/10

CPC classification number: G11C16/3436 ,  G11C16/26 ,  G11C7/1084 ,  G11C7/1057 ,  G11C16/10

Abstract: A system includes a memory component and a processing device, operatively coupled with the memory component, to send a read command to the memory component while a program or erase operation being executed by the memory component is suspended. The processing device, operatively coupled with the memory component, can then send an auto resume command to the memory component to automatically resume execution of the program or erase operation after the read command is executed.

公开(公告)号：US20230325323A1

公开(公告)日：2023-10-12

申请号：US18178105

申请日：2023-03-03

Applicant: Micron Technology, Inc.

Inventor： Sushanth Bhushan ,  Dheeraj Srinivasan

IPC: G06F12/0891

CPC classification number: G06F12/0891

Abstract: Control logic in a memory device executes a first programming operation to program the set of memory cells to a set of programming levels. A first cache ready signal is generated, the first cache ready signal indicating to a host system to send first data associated with a second programming operation to an input/output (I/O) data cache of the memory device. A first encoded data value and a second encoded data value associated with each memory cell of the set of memory cells are generated. A second cache ready signal is generated, the second cache ready signal indicating to the host system to send second data associated with the next programming operation to the I/O data cache. The first data associated with the second programming operation is caused to be stored in a third data cache of the cache storage. A third cache ready signal is generated, the third cache ready signal indicating to the host system to send third data associated with the second programming operation to the I/O data cache.