BUILD-UP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME

    公开(公告)号:US20230005802A1

    公开(公告)日:2023-01-05

    申请号:US17843799

    申请日:2022-06-17

    Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

    Build-up package for integrated circuit devices, and methods of making same

    公开(公告)号:US11367667B2

    公开(公告)日:2022-06-21

    申请号:US16819486

    申请日:2020-03-16

    Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

    Overlapping die stacks for NAND package architecture

    公开(公告)号:US11309281B2

    公开(公告)日:2022-04-19

    申请号:US17003789

    申请日:2020-08-26

    Abstract: A semiconductor device assembly includes a substrate having a plurality of external connections, a first stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.

    NOVEL BUILD-UP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME

    公开(公告)号:US20200286801A1

    公开(公告)日:2020-09-10

    申请号:US16819486

    申请日:2020-03-16

    Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

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